Noise analysis of non-linear dynamic integrated circuits. - Amir Zjajo; Qin Tang; Michel Berkelaar; Nick van der Meijs (CICC, 2010)

RDE-based transistor-level gate simulation for statistical static timing analysis. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (DAC, 2010)

Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (PATMOS, 2010)

Statistical Moment Estimation of Delay and Power in Circuit Simulation. - Ashish Nigam; Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (J. Low Power Electron., 2010)

Pseudo circuit model for representing uncertainty in waveforms. - Ashish Nigam; Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (DATE, 2011)

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs. - Amir Zjajo; Qin Tang; Michel Berkelaar; José Pineda de Gyvez; Alessandro Di Bucchianico; Nick van der Meijs (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Crosstalk-aware statistical interconnect delay calculation. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (ASP-DAC, 2012)

Transistor-level gate model based statistical timing analysis considering correlations. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (DATE, 2012)

Direct Statistical Simulation of Timing Properties in Sequential Circuits. - Javier Rodríguez; Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (PATMOS, 2012)

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver. - Qin Tang; Javier Rodríguez; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Considering Crosstalk Effects in Statistical Timing Analysis. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)