Throughout Analysis and Configuration Design of a Shared-Resource Multiprocessor System: PUMPS. - Faye A. Briggs; Michel Dubois 001; Kai Hwang 001 (ISCA, 1981)

Efficient Interprocessor Communications for MIMD Multiprocessor Systems. - Michel Dubois 001; Faye A. Briggs (ISCA, 1981)

Performance of Cache-Based Multiprocessors. - Faye A. Briggs; Michel Dubois 001 (SIGMETRICS, 1981)

An approximate analytical model for asynchronous processes in multiprocessors. - Michel Dubois 001; Faye A. Briggs (ICPP, 1982)

Effects of Cache Coherency in Multiprocessors. - Michel Dubois 001; Faye A. Briggs (IEEE Trans. Computers, 1982)

Performance of Synchronized Iterative Processes in Multiprocessor Systems. - Michel Dubois 001; Faye A. Briggs (IEEE Trans. Software Eng., 1982)

Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories. - Faye A. Briggs; Michel Dubois 001 (IEEE Trans. Computers, 1983)

A Cache-Based Multiprocessor with High Efficiency. - Michel Dubois 001 (IEEE Trans. Computers, 1985)

Generalized Asynchronous Iterations. - Aydin Üresin; Michel Dubois 001 (CONPAR, 1986)

Trace-Driven Simulations of Parallel and Distributed Algorithms in Multiprocessors. - Michel Dubois 001; Faye A. Briggs; Indira Patil; Meera Balakrishnan (ICPP, 1986)

The TX16: A Highly Programmable Multi-microprocessor Architecture. - Jean-Luc Gaudiot; Michel Dubois 001; Liang-Teh Lee; Nadim G. Tohme (IEEE Micro, 1986)

Effect of Invalidations on the Hit Ratio of Cache-Based Multiprocessors. - Michel Dubois 001 (ICPP, 1987)

Asynchronous Relaxation of Non-Numerical Data. - Aydin Üresin; Michel Dubois 001 (ICPP, 1987)

Correct Memory Operation of Cache-Based Multiprocessors. - Christoph Scheurich; Michel Dubois 001 (ISCA, 1987)

Shared Data Contention in a Cache Coherence Protocol. - Michel Dubois 001; Jin-Chin Wang (ICPP (1), 1988)

Concurrent Miss Resolution in Multiprocessor Caches. - Christoph Scheurich; Michel Dubois 001 (ICPP (1), 1988)

The design of a lockup-free cache for high-performance multiprocessors. - Christoph Scheurich; Michel Dubois 001 (SC, 1988)

Synchronization, Coherence, and Event Ordering in Multiprocessors. - Michel Dubois 001; Christoph Scheurich; Faye A. Briggs (Computer, 1988)

Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses. - Michel Dubois 001 (IEEE Trans. Computers, 1988)

Sufficient conditions for the convergence of asynchronous iterations. - Aydin Üresin; Michel Dubois 001 (Parallel Comput., 1989)

Dynamic Page Migration in Multiprocessors with Distributed Global Memory. - Christoph Scheurich; Michel Dubois 001 (IEEE Trans. Computers, 1989)

Transient Models of Bus-Based Multiprocessors. - Anastasios A. Economides; Michel Dubois 001 (ICPP (1), 1990)

Algorithm-Driven Simulation and Performance Projection of a RISC-based Orthogonal Multiprocessor. - Sharad Mehrotra; Chien-Ming Cheng; Kai Hwang 001; Michel Dubois 001; Dhabaleswar K. Panda 001 (ICPP (3), 1990)

Asynchronous Iterations with Bounded Delay. - Aydin Üresin; Michel Dubois 001 (ICPP (3), 1990)

OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses. - Kai Hwang 001; Michel Dubois 001; Dhabaleswar K. Panda 001; S. Rao; Shisheng Shang; Aydin Üresin; W. Mao; H. Nair; M. Lytwyn; F. Hsieh; J. Liu; Sharad Mehrotra; et al. (ICS, 1990)

Cache Architectures in Tightly Coupled Multiprocessors - Guest Editors' Introduction to the Special Issue. - Michel Dubois 001; Shreekant S. Thakkar (Computer, 1990)

Scalable Shared-Memory Multiprocessor Architectures. - Shreekant S. Thakkar; Michel Dubois 001; Anthony T. Laundrie; Gurindar S. Sohi; David V. James; Stein Gjessing; Manu Thapar; Bruce Delagi; Michael J. Carlton; Alvin M. Despain (Computer, 1990)

Performance comparison of cache coherence protocols based on the access burst model. - Jin-Chin Wang; Michel Dubois 001 (Comput. Syst. Sci. Eng., 1990)

Memory Access Dependencies in Shared-Memory Multiprocessors. - Michel Dubois 001; Christoph Scheurich (IEEE Trans. Software Eng., 1990)

Parallel Asynchronous Algorithms for Discrete Data - Aydin Üresin; Michel Dubois 001 (J. ACM, 1990)

Cache Coherence on a Slotted Ring. - Luiz André Barroso; Michel Dubois 001 (ICPP (1), 1991)

Analytical Modeling for Finite Cache Effects. - Jin-Chin Wang; Michel Dubois 001; Faye A. Briggs (ICPP (1), 1991)

Delayed consistency and its effects on the miss rate of parallel programs. - Michel Dubois 001; Jin-Chin Wang; Luiz André Barroso; Kangwoo Lee; Yung-Syau Chen (SC, 1991)

Lockup-free Caches in High-Performance Multiprocessors. - Christoph Scheurich; Michel Dubois 001 (J. Parallel Distributed Comput., 1991)

The Run-Time Efficiency of Parallel Asynchronous Algorithms. - Michel Dubois 001; Faye A. Briggs (IEEE Trans. Computers, 1991)

Shared Block Contention in a Cache Coherence Protocol. - Michel Dubois 001; Jin-Chin Wang (IEEE Trans. Computers, 1991)

Matching Algorithms and Architecture in Hierarchical Shared-Memory Multiprocessor (HMS) Systems. - Ashfaq A. Khokhar; Michel Dubois 001 (IPPS, 1992)

Scalability Problems in Multiprocessors with Private Caches. - Michel Dubois 001; Luiz André Barroso; Yung-Syau Chen; Koray Öner (PARLE, 1992)

Special Issue on Memory System Architectures for Scalable Multiprocessors. - Michel Dubois 001 (J. Parallel Distributed Comput., 1992)

Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. - Fredrik Dahlgren; Michel Dubois 001; Per Stenström (ICPP (1), 1993)

Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures. - Koray Öner; Michel Dubois 001 (International Conference on Supercomputing, 1993)

Cache Protocols with Partial Block Invalidations. - Yung-Syau Chen; Michel Dubois 001 (IPPS, 1993)

The Performance of Cache-Coherent Ring-based Multiprocessors. - Luiz André Barroso; Michel Dubois 001 (ISCA, 1993)

The Detection and Elimination of Useless Misses in Multiprocessors. - Michel Dubois 001; Jonas Skeppstedt; Livio Ricciulli; Krishnan Ramamurthy; Per Stenström (ISCA, 1993)

Cache Inclusion and Processor Sampling in Multiprocessor Simulations. - Jacqueline Chame; Michel Dubois 001 (SIGMETRICS, 1993)

The Verification of Cache Coherence Protocols. - Fong Pong; Michel Dubois 001 (SPAA, 1993)

Correctness of a Directory-Based Cache Coherence Protocol: Early Experience. - Fong Pong; Michel Dubois 001 (SPDP, 1993)

An Integrated Methodology for the Verification of Directory-Based Cache Protocols. - Fong Pong; Per Stenström; Michel Dubois 001 (ICPP (1), 1994)

Combined Performance Gains of Simple Cache Protocol Extensions. - Fredrik Dahlgren; Michel Dubois 001; Per Stenström (ISCA, 1994)

Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study. - Fong Pong; Andreas Nowatzyk; Gunes Aybay; Michel Dubois 001 (Euro-Par, 1995)

The Design of RPM: An FPGA-based Multiprocessor Emulator. - Koray Öner; Luiz André Barroso; Sasan Iman; Jaeheon Jeong; Krishnan Ramamurthy; Michel Dubois 001 (FPGA, 1995)

RPM: A Rapid Prototyping Engine for Multiprocessor Systems. - Luiz André Barroso; Sasan Iman; Jaeheon Jeong; Koray Öner; Michel Dubois 001 (Computer, 1995)

Implementation and evaluation of update-based cache protocols under relaxed memory consistency models. - Håkan Grahn; Per Stenström; Michel Dubois 001 (Future Gener. Comput. Syst., 1995)

Essential Misses and Data Traffic in Coherence Protocols. - Michel Dubois 001; Jonas Skeppstedt; Per Stenström (J. Parallel Distributed Comput., 1995)

Performance Evaluation of the Slotted Ring Multiprocessor. - Luiz André Barroso; Michel Dubois 001 (IEEE Trans. Computers, 1995)

Sequential Hardware Prefetching in Shared-Memory Multiprocessors. - Fredrik Dahlgren; Michel Dubois 001; Per Stenström (IEEE Trans. Parallel Distributed Syst., 1995)

A New Approach for the Verification of Cache Coherence Protocols. - Fong Pong; Michel Dubois 001 (IEEE Trans. Parallel Distributed Syst., 1995)

Performance of Asynchronous Linear Iterations with Random Delays. - Adrian Moga; Michel Dubois 001 (IPPS, 1996)

Formal Verification of Delayed Consistency Protocols. - Fong Pong; Michel Dubois 001 (IPPS, 1996)

Effects of Asynchronism on the Convergence Rate of Iterative Algorithms. - Aydin Üresin; Michel Dubois 001 (J. Parallel Distributed Comput., 1996)

Bottleneck-Free Interconnect and IO Subsystem in SPAX. - Kangwoo Lee; Woo-Jong Han; Michel Dubois 001 (ICPADS, 1997)

Hardware Versus Software Implementation of COMA. - Adrian Moga; Michel Dubois 001; Alain Gefflaut (ICPP, 1997)

Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps. - Jonas Skeppstedt; Michel Dubois 001 (ICPP, 1997)

Boosting the Performance of Shared Memory Multiprocessors. - Per Stenström; Mats Brorsson; Fredrik Dahlgren; Håkan Grahn; Michel Dubois 001 (Computer, 1997)

Verification Techniques for Cache Coherence Protocols. - Fong Pong; Michel Dubois 001 (ACM Comput. Surv., 1997)

Virtual-address caches. Part 1: problems and solutions in uniprocessors. - Michel Cekleov; Michel Dubois 001 (IEEE Micro, 1997)

Virtual-address caches.2. Multiprocessor issues. - Michel Cekleov; Michel Dubois 001 (IEEE Micro, 1997)

The Effectiveness of SRAM Network Caches in Clustered DSMs. - Adrian Moga; Michel Dubois 001 (HPCA, 1998)

Retrospective: Memory Access Buffering in Multiprocessors. - Michel Dubois 001; Christoph Scheurich (25 Years ISCA: Retrospectives and Reprints, 1998)

Memory Access Buffering in Multiprocessors. - Michel Dubois 001; Christoph Scheurich; Faye A. Briggs (25 Years ISCA: Retrospectives and Reprints, 1998)

Options for Dynamic Address Translation in COMAs. - Xiaogang Qiu; Michel Dubois 001 (ISCA, 1998)

In-Memory Directories: Eliminating the Cost of Directories in CC-NUMAs. - Christopher Ho; Heidi E. Ziegler; Michel Dubois 001 (SPAA, 1998)

Rapid Hardware Prototyping on RPM-2. - Michel Dubois 001; Jaeheon Jeong; Yong Ho Song; Adrian Moga (IEEE Des. Test Comput., 1998)

Formal Verification of Complex Coherence Protocols Using Symbolic State Models. - Fong Pong; Michel Dubois 001 (J. ACM, 1998)

Empirical Models of Miss Rates. - Kangwoo Lee; Michel Dubois 001 (Parallel Comput., 1998)

Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. - Fredrik Dahlgren; Michel Dubois 001; Per Stenström (IEEE Trans. Computers, 1998)

Design Verification of the S3.mp Cache-Coherent Shared-Memory System. - Fong Pong; Michael C. Browne; Gunes Aybay; Andreas Nowatzyk; Michel Dubois 001 (IEEE Trans. Computers, 1998)

Tolerating Late Memory Traps in ILP Processors. - Xiaogang Qiu; Michel Dubois 001 (ISCA, 1999)

Optimal Replacements in Caches with Two Miss Costs. - Jaeheon Jeong; Michel Dubois 001 (SPAA, 1999)

Compiler Controlled Prefetching for Multiprocessors Using Low-Overhead Traps and Prefetch Engines. - Jonas Skeppstedt; Michel Dubois 001 (J. Parallel Distributed Comput., 2000)

Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models. - Fong Pong; Michel Dubois 001 (IEEE Trans. Parallel Distributed Syst., 2000)

Towards Virtually-Addressed Memory Hierarchies. - Xiaogang Qiu; Michel Dubois 001 (HPCA, 2001)

The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. - Martin Kämpe; Per Stenström; Michel Dubois 001 (HPCA, 2002)

Shared cache architectures for decision support systems. - Michel Dubois 001; Jaeheon Jeong; Ashwini K. Nanda (Perform. Evaluation, 2002)

Cost-Sensitive Cache Replacement Algorithms. - Jaeheon Jeong; Michel Dubois 001 (HPCA, 2003)

Integrating complete-system and user-level performance/power simulators: the SimWattch approach. - Jianwei Chen; Michel Dubois 001; Per Stenström (ISPASS, 2003)

Scalability implications of software-implemented coherence. - Adrian Moga; Michel Dubois 001 (Comput. Syst. Sci. Eng., 2003)

Fighting the memory wall with assisted execution. - Michel Dubois 001 (Conf. Computing Frontiers, 2004)

Self-correcting LRU replacement policies. - Martin Kämpe; Per Stenström; Michel Dubois 001 (Conf. Computing Frontiers, 2004)

Tolerating Late Memory Traps in Dynamically Scheduled Processors. - Xiaogang Qiu; Michel Dubois 001 (IEEE Trans. Computers, 2004)

Controlling leakage power with the replacement policy in slumberous caches. - Nasir Mohyuddin; Rashed Zafar Bhatti; Michel Dubois 001 (Conf. Computing Frontiers, 2005)

Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors. - Xiaogang Qiu; Michel Dubois 001 (IEEE Trans. Parallel Distributed Syst., 2005)

Simple penalty-sensitive replacement policies for caches. - Jaeheon Jeong; Per Stenström; Michel Dubois 001 (Conf. Computing Frontiers, 2006)

Cache Replacement Algorithms with Nonuniform Miss Costs. - Jaeheon Jeong; Michel Dubois 001 (IEEE Trans. Computers, 2006)

Loop-level Speculative Parallelism in Embedded Applications. - Md. Mafijul Islam; Alexander Busck; Mikael Engbom; Simji Lee; Michel Dubois 001; Per Stenström (ICPP, 2007)

STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems. - Michel Dubois 001; Hyunyoung Lee 001; Lan Lin (IPDPS, 2007)

SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. - Jianwei Chen; Michel Dubois 001; Per Stenström (IEEE Micro, 2007)

STAMP: A universal algorithmic model for next-generation multithreaded machines and systems. - Michel Dubois 001; Hyunyoung Lee 001 (IPDPS, 2008)

Simple Penalty-Sensitive Cache Replacement Policies. - Jaeheon Jeong; Per Stenström; Michel Dubois 001 (J. Instr. Level Parallelism, 2008)

The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches. - Xiaogang Qiu; Michel Dubois 001 (IEEE Trans. Computers, 2008)

Exploiting Simulation Slack to Improve Parallel Simulation Speed. - Jianwei Chen; Murali Annavaram; Michel Dubois 001 (ICPP, 2009)

Dynamic MIPS rate stabilization in out-of-order processors. - Jinho Suh; Michel Dubois 001 (ISCA, 2009)

A comparative evaluation of hybrid distributed shared-memory systems. - Adrian Moga; Michel Dubois 001 (J. Syst. Archit., 2009)

SlackSim: a platform for parallel simulations of CMPs on CMPs. - Jianwei Chen; Murali Annavaram; Michel Dubois 001 (SIGARCH Comput. Archit. News, 2009)

Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors. - Woojin Choi; Seok-Jun Park; Michel Dubois 001 (Trans. High Perform. Embed. Archit. Compil., 2009)

Adaptive and Speculative Slack Simulations of CMPs on CMPs. - Jianwei Chen; Lakshmi Kumar Dabbiru; Daniel Wong 001; Murali Annavaram; Michel Dubois 001 (MICRO, 2010)

CPPC: correctable parity protected cache. - Mehrtash Manoochehri; Murali Annavaram; Michel Dubois 001 (ISCA, 2011)

Soft error benchmarking of L2 caches with PARMA. - Jinho Suh; Mehrtash Manoochehri; Murali Annavaram; Michel Dubois 001 (SIGMETRICS, 2011)

MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit Upsets. - Jinho Suh; Murali Annavaram; Michel Dubois 001 (HPCA, 2012)

PHYS: Profiled-HYbrid Sampling for soft error reliability benchmarking. - Jinho Suh; Murali Annavaram; Michel Dubois 001 (DSN, 2013)

Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures. - Waleed Dweik; Murali Annavaram; Michel Dubois 001 (DATE, 2014)

Extremely Low Cost Error Protection with Correctable Parity Protected Cache. - Mehrtash Manoochehri; Murali Annavaram; Michel Dubois 001 (IEEE Trans. Computers, 2014)

Chip-independent Error Correction in main memories. - Mehrtash Manoochehri; Michel Dubois 001 (SAMOS, 2015)

Dynamic MIPS Rate Stabilization for Complex Processors. - Jinho Suh; Chieh-Ting Huang; Michel Dubois 001 (ACM Trans. Archit. Code Optim., 2015)

Power Efficient Hardware Transactional Memory: Dynamic Issue of Transactions. - Sang Wook Stephen Do; Michel Dubois 001 (ACM Trans. Archit. Code Optim., 2016)

Accurate Model for Application Failure Due to Transient Faults in Caches. - Mehrtash Manoochehri; Michel Dubois 001 (IEEE Trans. Computers, 2016)

Core Reliability: Leveraging Hardware Transactional Memory. - Sang Wook Stephen Do; Michel Dubois 001 (IEEE Comput. Archit. Lett., 2018)

Transaction-Based Core Reliability. - Sang Wook Stephen Do; Michel Dubois 001 (IPDPS, 2020)