A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. - Matheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans (ASYNC, 2014)

A design flow for physical synthesis of digital cells with ASTRAN. - Adriel Ziesemer; Ricardo Reis 001; Matheus T. Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans (ACM Great Lakes Symposium on VLSI, 2014)

Automatic layout synthesis with ASTRAN applied to asynchronous cells. - Adriel Ziesemer; Ricardo Reis 001; Matheus T. Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans (LASCAS, 2014)

Automated Synthesis of Cell Libraries for Asynchronous Circuits. - Matheus Trevisan; Michel Evandro Arendt; Adriel Ziesemer; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans (SBCCI, 2014)

Static Differential NCL Gates: Toward Low Power. - Matheus Trevisan Moreira; Michel Evandro Arendt; Fernando Gehm Moraes; Ney Laert Vilar Calazans (IEEE Trans. Circuits Syst. II Express Briefs, 2015)