High-level synthesis and codesign methods: an application to a videophone codec. - Pierre G. Paulin; Jean Fréhel; Michel Harrand; Elisabeth Berrebi; Clifford Liem; François Naçabal; Jean-Claude Herluison (EURO-DAC, 1995)

A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller. - Michel Harrand; Jose Sanches; Alain Bellon; Joseph Bulone; Alain Tournier; Olivier Deygas; Jean-Claude Herluison; David Doise; Elisabeth Berrebi (IEEE J. Solid State Circuits, 1999)

A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM. - Andrew Cofler; Francois Druilhe; Denis Dutoit; Michel Harrand (IEEE J. Solid State Circuits, 2006)

Multimedia and Parrallel Signal Processors. - Michel Harrand; Liang-Gee Chen (ISSCC, 2007)

Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor. - Pascal Aubry; Pierre-Edouard Beaucamps; Frédéric Blanc 001; Bruno Bodin; Sergiu Carpov; Loïc Cudennec; Vincent David; Philippe Dore; Paul Dubrulle; Benoît Dupont de Dinechin; François Galea; Thierry Goubier; et al. (ICCS, 2013)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)