Experimental multiprocessor architecture dedicated for solving 3D PDEs. - J.-M. Libs; B. Siaud; Jean Durupt; Bernard Boutherin; Gilles Jacquemod; Michel Le Helley (PDP, 1993)

Automatic layout generation for CMOS analog transistors. - Hervé Mathias; Josette Berger-Toussan; Frédéric Gaffiot; L. Hébrard; Gilles Jacquemod; Michel Le Helley (EURO-DAC, 1994)

FLAG: a flexible layout generator for analog MOS transistors. - Hervé Mathias; Josette Berger-Toussan; Gilles Jacquemod; Frédéric Gaffiot; Michel Le Helley (IEEE J. Solid State Circuits, 1998)