Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. - Michele Portolan; Régis Leveugle (IOLTS, 2004)

Towards a Secure and Reliable System. - Michele Portolan; Régis Leveugle (EUC, 2005)

On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. - Michele Portolan; Régis Leveugle (IOLTS, 2005)

Effective Checkpoint and Rollback Using Hardware/OS Collaboration. - Michele Portolan; Régis Leveugle (DFT, 2007)

Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system. - Pierre Vanhauwaert; Michele Portolan; Régis Leveugle; Philippe Roche (ICECS, 2008)

A New Language Approach for IJTAG. - Michele Portolan; Suresh Goyal; Bradford G. Van Treuren; Chen-Huan Chiang; Tapan J. Chakraborty; Thomas B. Cook (ITC, 2008)

Scalable and efficient integrated test architecture. - Michele Portolan; Suresh Goyal; Bradford G. Van Treuren (ITC, 2009)

Scan chain securization though Open-Circuit Deadlocks. - Michele Portolan; Bradford G. Van Treuren; Suresh Goyal (ITC, 2010)

A Common Language Framework for Next-Generation Embedded Testing. - Michele Portolan; Suresh Goyal; Bradford G. Van Treuren; Chen-Huan Chiang; Tapan J. Chakraborty; Thomas B. Cook (IEEE Des. Test Comput., 2010)

Packet-based JTAG for remote testing. - Michele Portolan (ITC, 2012)

Special session 8A: E.J. McCluskey doctoral thesis award semi-final - presentations. - Michele Portolan; Michail Maniatakos (VTS, 2013)

Special session 3B: E.J. McCluskey Doctoral Thesis Award semi-final - Posters. - Michele Portolan; Michail Maniatakos (VTS, 2013)

Automatic equivalent model generation and evolution for small cell networks. - Davide Cherubini; Michele Portolan (WiOpt, 2013)

Executing IJTAG: Are Vectors Enough? - Michele Portolan; Bradford G. Van Treuren; Suresh Goyal (IEEE Des. Test, 2013)

Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options. - K. Chibani; Salma Bergaoui; Michele Portolan; Régis Leveugle (ICECS, 2014)

Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor. - K. Chibani; Mohamed Ben Jrad; Michele Portolan; Régis Leveugle (VLSI-SoC, 2014)

Special session 8A: E.J. McCluskey Doctoral Thesis Award semi-final. - Michele Portolan; Michail Maniatakos (VTS, 2014)

Special session 8C: E.J. McCluskey doctoral thesis award semi-final. - Michele Portolan; K. Huang (VTS, 2015)

A novel test generation and application flow for functional access to IEEE 1687 instruments. - Michele Portolan (ETS, 2016)

Student-driven development of a digital tester. - Michele Portolan; Robin Rolland (EWME, 2016)

Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations. - K. Chibani; Michele Portolan; Régis Leveugle (IOLTS, 2016)

Accessing 1687 systems using arbitrary protocols. - Michele Portolan (ITC, 2016)

Mixed-signal BIST computation offloading using IEEE 1687. - Michele Portolan; Manuel J. Barragán; Rshdee Alhakim; Salvador Mir (ETS, 2017)

Reliability of computing systems: From flip flops to variables. - Giorgio Di Natale; Maha Kooli; Alberto Bosio; Michele Portolan; Régis Leveugle (IOLTS, 2017)

A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks. - Michele Portolan; Riccardo Cantoro; Ernesto Sánchez 001 (ETS, 2019)

Alternatives to Fault Injections for Early Safety/Security Evaluations. - Michele Portolan; Alessandro Savino; Régis Leveugle; Stefano Di Carlo; Alberto Bosio; Giorgio Di Natale (ETS, 2019)

Approximate computing design exploration through data lifetime metrics. - Alessandro Savino; Michele Portolan; Régis Leveugle; Stefano Di Carlo (ETS, 2019)

Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. - Aleksa Damljanovic; Artur Jutman; Michele Portolan; Ernesto Sánchez 001; Giovanni Squillero; Anton Tsertov (ITC, 2019)

Linking Chip, Board, and System Test via Standards. - Michele Portolan; Jeff Rearick; Martin Keim (ETS, 2020)

Dynamic Authentication-Based Secure Access to Test Infrastructure. - Michele Portolan; Vincent Reynaud; Paolo Maistri; Régis Leveugle (ETS, 2020)

A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. - Michele Portolan; R. Silveira Feitoza; Ghislain Takam Tchendjou; Vincent Reynaud; Kalpana Senthamarai Kannan; Manuel J. Barragán; Emmanuel Simeu; Paolo Maistri; Lorena Anghel; Régis Leveugle; Salvador Mir (IOLTS, 2020)

New Perspectives on Core In-field Path Delay Test. - Riccardo Cantoro; Dario Foti; Sandro Sartoni; Matteo Sonza Reorda; Lorena Anghel; Michele Portolan (ITC, 2020)

Modeling Novel Non-JTAG IEEE 1687-Like Architectures. - Mike Laisne; Alfred L. Crouch; Michele Portolan; Martin Keim; Hans Martin von Staudt; M. Abdalwahab; Bradford G. Van Treuren; Jeff Rearick (ITC, 2020)

Automated Testing Flow: The Present and the Future. - Michele Portolan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces. - Hans Martin von Staudt; Bradford G. Van Treuren; Jeff Rearick; Michele Portolan; Martin Keim (ETS, 2021)

Security EDA Extension through P1687.1 and 1687 Callbacks. - Michele Portolan; Vincent Reynaud; Paolo Maistri; Régis Leveugle; Giorgio Di Natale (ITC, 2021)

Secure Test with RSNs: Seamless Authenticated Extended Confidentiality. - Paolo Maistri; Vincent Reynaud; Michele Portolan; Régis Leveugle (NEWCAS, 2021)

IEEE P1687.1: Extending the Network Boundaries for Test. - Michael Laisne; Alfred L. Crouch; Michele Portolan; Martin Keim; Hans Martin von Staudt; Bradford G. Van Treuren; Jeff Rearick; Songlin Zuo (ITC, 2022)

Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure. - Michele Portolan; Antonios Pavlidis; Giorgio Di Natale; Eric Faehn; Haralampos-G. Stratigopoulos (ITC, 2022)

Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions. - Michele Portolan; Emanuele Valea; Paolo Maistri; Giorgio Di Natale (IEEE Des. Test, 2022)

Evaluating the Impact of Aging on Path-Delay Self-Test Libraries. - Riccardo Cantoro; Sandro Sartoni; Matteo Sonza Reorda; Lorena Anghel; Michele Portolan (DFT, 2023)

Refreshing the JTAG Family. - Michele Portolan; Martin Keim; Jeff Rearick; Heiko Ehrenberg (VTS, 2023)

Self-Test Library Generation for In-Field Test of Path Delay Faults. - Lorena Anghel; Riccardo Cantoro; Riccardo Masante; Michele Portolan; Sandro Sartoni; Matteo Sonza Reorda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

What Would Interactive Testing With 1687 Look Like? - Michele Portolan; Martin Keim; J. F. Coté; Hans-Martin Von Staud (ETS, 2024)

True Interactive Testing Based on IJTAG. - Michele Portolan (IEEE Des. Test, 2024)