Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate. - Hasan Ymeri; Bart Nauwelaers; Karen Maex; David De Roest; Michele Stucchi; Servaas Vandenberghe (DATE, 2002)

Interconnect exploration for future wire dominated technologies. - Antonis Papanikolaou; Miguel Miranda; Francky Catthoor; Henk Corporaal; Hugo De Man; David De Roest; Michele Stucchi; Karen Maex (SLIP, 2002)

Frequency dependence in interline capacitance measurements. - Michele Stucchi; Karen Maex (IEEE Trans. Instrum. Meas., 2002)

Global interconnect trade-off for technology over memory modules to application level: case study. - Antonis Papanikolaou; Miguel Miranda; Francky Catthoor; Henk Corporaal; Hugo De Man; David De Roest; Michele Stucchi; Karen Maex (SLIP, 2003)

Interconnect width selection for deep submicron designs using the table lookup method. - Mandeep Bamal; Evelyn Grossar; Michele Stucchi; Karen Maex (SLIP, 2004)

Statistically Aware SRAM Memory Array Design. - Evelyn Grossar; Michele Stucchi; Karen Maex; Wim Dehaene (ISQED, 2006)

Impact of interconnect resistance increase on system performance of low power and high performance designs. - Mandeep Bamal; Youssef Travaly; Wenqi Zhang; Michele Stucchi; Karen Maex (SLIP, 2006)

Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies. - Evelyn Grossar; Michele Stucchi; Karen Maex; Wim Dehaene (IEEE J. Solid State Circuits, 2006)

A tool flow for predicting system level timing failures due to interconnect reliability degradation. - Jin Guo 001; Antonis Papanikolaou; Michele Stucchi; Kristof Croes; Zsolt Tokei; Francky Catthoor (ACM Great Lakes Symposium on VLSI, 2008)

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). - Jan Van Olmen; Jan Coenen; Wim Dehaene; Kristin De Meyer; Cedric Huyghebaert; Anne Jourdain; Guruprasad Katti; Abdelkarim Mercha; Michal Rakowski; Michele Stucchi; Youssef Travaly; Eric Beyne; et al. (3DIC, 2009)

Impact of 3D design choices on manufacturing cost. - Dimitrios Velenis; Michele Stucchi; Erik Jan Marinissen; Bart Swinnen; Eric Beyne (3DIC, 2009)

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot. - Paul Marchal; Bruno Bougard; Guruprasad Katti; Michele Stucchi; Wim Dehaene; Antonis Papanikolaou; Diederik Verkest; Bart Swinnen; Eric Beyne (Proc. IEEE, 2009)

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. - Geert Van der Plas; Steven Thijs; Dimitri Linten; Guruprasad Katti; Paresh Limaye; Abdelkarim Mercha; Michele Stucchi; Herman Oprins; Bart Vandevelde; Nikolaos Minas; Miro Cupac; Morin Dehan; et al. (CICC, 2010)

3D integration: Circuit design, test, and reliability challenges. - Nikolaos Minas; Ingrid De Wolf; Erik Jan Marinissen; Michele Stucchi; Herman Oprins; Abdelkarim Mercha; Geert Van der Plas; Dimitrios Velenis; Pol Marchal (IOLTS, 2010)

Design issues and considerations for low-cost 3D TSV IC technology. - Geert Van der Plas; Paresh Limaye; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Domae Shinichi; Vladimir Cherman; et al. (ISSCC, 2010)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Geert Van der Plas; Paresh Limaye; Igor Loi; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Vladimir Cherman; et al. (IEEE J. Solid State Circuits, 2011)

Fine grain thermal modeling and experimental validation of 3D-ICs. - Herman Oprins; Adi Srinivasan; Miroslav Cupák; Vladimir Cherman; Cristina Torregiani; Michele Stucchi; Geert Van der Plas; Paul Marchal; Bart Vandevelde; E. Cheng (Microelectron. J., 2011)

Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique. - Michele Stucchi; Dimitrios Velenis; Guruprasad Katti (IEEE Trans. Instrum. Meas., 2012)

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias. - Yunlong Li; Stefaan Van Huylenbroeck; Els Van Besien; Xiaoping Shi; Chen Wu; Michele Stucchi; Gerald Beyer; Eric Beyne; Ingrid De Wolf; Kristof Croes (Microelectron. Reliab., 2014)

Impact of interconnect multiple-patterning variability on SRAMs. - Ioannis Karageorgos; Michele Stucchi; Praveen Raghavan; Julien Ryckaert; Zsolt Tokei; Diederik Verkest; Rogier Baert; Sushil Sakhare; Wim Dehaene (DATE, 2015)

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. - Stefaan Van Huylenbroeck; Yunlong Li; Michele Stucchi; Lieve Bogaerts; Joeri De Vos; Gerald Beyer; Eric Beyne; Mohand Brouri; Praveen Nalla; Sanjay Gopinath; Matthew Thorum; Joe Richardson; et al. (3DIC, 2016)

Reliability Challenges Related to TSV Integration and 3-D Stacking. - Kristof Croes; Joke De Messemaeker; Yunlong Li; Wei Guo; Olalla Varela Pedreira; Vladimir Cherman; Michele Stucchi; Ingrid De Wolf; Eric Beyne (IEEE Des. Test, 2016)

Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices. - Kristof J. P. Jacobs; T. Wang; Michele Stucchi; Mario Gonzalez; Kris Croes; Ingrid De Wolf; Eric Beyne (Microelectron. Reliab., 2017)

TSV process-induced MOS reliability degradation. - Yunlong Li; Michele Stucchi; Stefaan Van Huylenbroeck; Geert Van der Plas; Gerald Beyer; Eric Beyne; Kristof Croes (IRPS, 2018)

Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. - Erik Jan Marinissen; Ferenc Fodor; Arnita Podpod; Michele Stucchi; Yu-Rong Jian; Cheng-Wen Wu (ITC, 2018)

Understanding EM-Degradation Mechanisms in Metal Heaters Used for Si Photonics Applications. - Kris Croes; Veerle Simons; Sofie Beyne; Vladimir Cherman; Herman Oprins; Michele Stucchi; Philippe Absil; A. Glabman; Eric Wilcox (IRPS, 2019)

Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios. - Michele Stucchi; Ferenc Fodor; Erik Jan Marinissen (ETS, 2020)

Metal reliability mechanisms in Ruthenium interconnects. - Olalla Varela Pedreira; Michele Stucchi; Anshul Gupta; Victor Vega-Gonzalez; Marleen van der Veen; Stephane Lariviere; Christopher J. Wilson; Zsolt Tökei; Kristof Croes (IRPS, 2020)

Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy. - Kristof J. P. Jacobs; Michele Stucchi; Eric Beyne (IEEE Trans. Instrum. Meas., 2021)

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. - Rongmei Chen; Giuliano Sisto; Michele Stucchi; Anne Jourdain; Kenichi Miyaguchi; Pieter Schuddinck; P. Woeltgens; H. Lin; Naveen Kakarla; Anabela Veloso; Dragomir Milojevic; Odysseas Zografos; et al. (VLSI Technology and Circuits, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. - Francesco Lorenzelli; Asser Elsayed; Clement Godfrin; Alexander Grill; Stefan Kubicek; Ruoyu Li; Michele Stucchi; Danny Wan; Kristiaan De Greve; Erik Jan Marinissen; Georges G. E. Gielen (ETS, 2023)

Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. - Francesco Lorenzelli; Asser Elsayed; Clement Godfrin; Alexander Grill; Stefan Kubicek; Ruoyu Li; Michele Stucchi; Danny Wan; Kristiaan De Greve; Erik Jan Marinissen; Georges G. E. Gielen (ITC, 2023)

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. - Giuliano Sisto; R. Preston; Rongmei Chen; Gioele Mirabelli; Anita Farokhnejad; Yun Zhou; Ivan Ciofi; Anne Jourdain; A. Veloso; Michele Stucchi; Odysseas Zografos; Pieter Weckx; et al. (VLSI Technology and Circuits, 2023)

Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. - P. Zhao; Liesbeth Witters; Anne Jourdain; Michele Stucchi; Nicolas Jourdan 002; J. W. Maes; H. Bana; C. Zhu; R. Chukka; F. Sebaai; Kevin Vandersmissen; N. Heylen; et al. (VLSI Technology and Circuits, 2024)

Impact of Al-doping on Al: HfO2Dielectric Reliability in MIM Capacitors. - C. Fohn; F. Zharfan; Emmanuel Chery; Kris Croes; Michele Stucchi; V. Afanas'ev (IRPS, 2025)