An explicit multi-exponential model for semiconductor junctions with series and shunt resistances. - Denise C. Lugo Muñoz; Juan Muci; Adelmo Ortiz-Conde; Francisco J. García-Sánchez; Michelly de Souza; Marcelo Antonio Pavanello (Microelectron. Reliab., 2011)

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs. - Michelly de Souza; Bruna Cardoso Paz; Denis Flandre; Marcelo Antonio Pavanello (Microelectron. Reliab., 2013)

Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors. - Rafael Assalti; Lígia Martins d'Oliveira; Marcelo Antonio Pavanello; Denis Flandre; Michelly de Souza (IET Circuits Devices Syst., 2016)

A new method for junctionless transistors parameters extraction. - Renan Trevisoli Doria; Rodrigo Trevisoli Doria; Michelly de Souza; Marcelo Antonio Pavanello; Sylvain Barraud (ESSDERC, 2017)

FOSS EKV2.6 Verilog-A Compact MOSFET Model. - Wladek Grabinski; Ahmed Abo-Elhadid; Marek Mierzwinski; Laurent Lemaitre; Mike Brinson; Christophe Lallement; Jean-Michel Sallese; Sadayuki Yoshitomi; Paul Malisse; Henri Oguey; Stefan Cserveny; Marcelo Antonio Pavanello; et al. (ESSDERC, 2019)

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors. - Michelly de Souza; Sylvain Barraud; Mikaël Cassé; Maud Vinet; Olivier Faynot; Marcelo Antonio Pavanello (ESSDERC, 2021)

Experimental Decomposition of the Carrier Mobility in the Conduction Planes of 2-Level Stacked Nanowires. - Giovanni Almeida Matos; Jaime CalÇade Rodrigues; Michelly de Souza; Mikaël Cassé; Sylvain Barraud; Olivier Faynot; Marcelo Antonio Pavanello (CCE, 2024)

Electrical Characterization of nMOSFETs from a 180 nm Commercial Technology at Low Temperatures. - Jessé de Oliveira; Marcelo Antonio Pavanello; Michelly de Souza (CCE, 2024)