ASIC CAD system based on hierarchical design-for-testability. - Michiaki Emori; Takashi Aikyo; Yasuhide Machida; Jun-ichi Shikatani (ITC, 1990)

ATREX : Design for Testability System for Mega Gate LSIs. - Michiaki Emori; Junko Kumagai; Koichi Itaya; Takashi Aikyo; Tomoko Anan; Junichi Niimi (Asian Test Symposium, 1997)

BIST-Aided Scan Test - A New Method for Test Cost Reduction. - Takahisa Hiraide; Kwame Osei Boateng; Hideaki Konishi; Koichi Itaya; Michiaki Emori; Hitoshi Yamanaka; Takashi Mochiyama (VTS, 2003)

The Application of BIST-Aided Scan Test for Real Chips. - Hideaki Konishi; Michiaki Emori; Takahisa Hiraide (ATS, 2006)

Test Data Compression of 100x for Scan-Based BIST. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Tatsuru Matsuo; Takahisa Hiraide; Hideaki Konishi; Michiaki Emori; Takashi Aikyo (ITC, 2006)

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Tatsuru Matsuo; Takahisa Hiraide; Hideaki Konishi; Michiaki Emori; Takashi Aikyo (IEICE Trans. Inf. Syst., 2008)