A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOS. - Jun Li; Hirohito Mukai; Mehmet Parlak; Michiaki Matsuo; James F. Buckwalter (CICC, 2013)

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication. - Vojkan Vidojkovic; Viki Szortyka; Khaled Khalaf; Giovanni Mangraviti; Steven Brebels; Wim Van Thillo; Kristof Vaesen; Bertrand Parvais; Vadim Issakov; Mike Libois; Michiaki Matsuo; John R. Long; et al. (ISSCC, 2013)