Logic simulation for LSI. - Kazuyuki Hirakawa; Noboru Shiraki; Michiaki Muraoka (DAC, 1982)

ACTAS: an accurate timing analysis system for VLSI. - Michiaki Muraoka; Hirokazu Iida; Hideyuki Kikuchihara; Michio Murakami; Kazuyuki Hirakawa (DAC, 1985)

A State Traversal Algorithm Using a State Covariance Matrix. - Akira Motohara; Toshinori Hosokawa; Michiaki Muraoka; Hidetsugu Maekawa; Kazuhiro Kayashima; Yasuharu Shimeki; Seichi Shin (DAC, 1993)

Design for testability using register-transfer level partial scan selection. - Akira Motohara; Sadami Takeoka; Toshinori Hosokawa; Mitsuyasu Ohta; Yuji Takai; Michihiro Matsumoto; Michiaki Muraoka (ASP-DAC, 1995)

A Design for testability Method Using RTL Partitioning. - Toshinori Hosokawa; Kenichi Kawaguchi; Mitsuyasu Ohta; Michiaki Muraoka (Asian Test Symposium, 1996)

A Partial Scan Design Method Based on n-Fold Line-up Structures. - Toshinori Hosokawa; Toshihiro Hiraoka; Mitsuyasu Ohta; Michiaki Muraoka; Shigeo Kuninobu (Asian Test Symposium, 1997)

A SoC Test Strategy Based on a Non-Scan DFT Method. - Hiroshi Date; Toshinori Hosokawa; Michiaki Muraoka (Asian Test Symposium, 2002)

A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. - Toshinori Hosokawa; Hiroshi Date; Michiaki Muraoka (Asian Test Symposium, 2002)

A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. - Toshinori Hosokawa; Hiroshi Date; Michiaki Muraoka (VTS, 2002)

VCDS tool demonstration. - Rafael K. Morizawa; Kazuo Tanaka; Keisuke Watanabe; Yuji Kaitsu; Shoji Hanamura; Takao Shinsha; Michiaki Muraoka (ASP-DAC, 2003)

VCore-based design methodology. - Michiaki Muraoka; Hideyuki Hamada; Hiroaki Nishi; Toshihiko Tada; Yoichi Onishi; Toshinori Hosokawa; Kenji Yoshida (ASP-DAC, 2003)

Synthesis for SoC architecture using VCores. - Hiroaki Nishi; Michiaki Muraoka; Rafael K. Morizawa; Hideaki Yokota; Hideyuki Hamada (ASP-DAC, 2003)

VCore-based platform for SoC design. - Yoichi Onishi; Michiaki Muraoka; Makoto Utsuki; Naoyuki Tsubaki (ASP-DAC, 2003)

A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. - Toshinori Hosokawa; Hiroshi Date; Masahide Miyazaki; Michiaki Muraoka; Hideo Fujiwara (Asian Test Symposium, 2003)

Design methodology for SoC arthitectures based on reusable virtual cores. - Michiaki Muraoka; Hiroaki Nishi; Rafael K. Morizawa; Hideaki Yokota; Hideyuki Hamada (ASP-DAC, 2004)

A DFT Selection Method for Reducing Test Application Time of System-on-Chips. - Masahide Miyazaki; Toshinori Hosokawa; Hiroshi Date; Michiaki Muraoka; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2004)

A multilayer crosstalk avoidance router using restricted maze grids. - Yoshiya Fujii; Michiaki Muraoka; Masahiko Toyonaga (MWSCAS, 2013)

A critical net reshape-router for high-performance VLSI layout design. - Yusuke Morimoto; Mitsuru Matsushita; Michiaki Muraoka; Masahiko Toyonaga (APCCAS, 2014)