Novel structure for high-speed multihighway serial-to-parallel converter. - Naoaki Yamanaka; Michihiro Hirata; Masao Suzuki; Takao Yano (IEEE Trans. Commun., 1988)

A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs. - Masao Suzaki; Naoki Yamanaka; Michihiro Hirata; Shiro Kikuchi (IEEE J. Solid State Circuits, 1990)

High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]. - Kiyoshi Ishii; Hideyuki Nosaka; Minoru Ida; Kenji Kurishima; Michihiro Hirata; Takatorno Enoki; Tsugumichi Shibata (ESSCIRC, 2004)

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. - Kiyoshi Ishii; Hideyuki Nosaka; Kimikazu Sano; Koichi Murata; Minoru Ida; Kenji Kurishima; Michihiro Hirata; Tsugumichi Shibata; Takatomo Enoki (IEEE J. Solid State Circuits, 2005)

An InP-Based 27-GHz-Bandwidth Limiting TIA IC Designed to Suppress Undershoot and Ringing in Its Output Waveform. - Hiroyuki Fukuyama; Michihiro Hirata; Kenji Kurishima; Minoru Ida; Masami Tokumitsu; Shogo Yamanaka; Munehiko Nagatani; Toshihiro Itoh; Kimikazu Sano; Hideyuki Nosaka; Koichi Murata (IEICE Trans. Electron., 2016)