A 4-Mbit DRAM with 16-bit concurrent ECC. - Toshio Yamada; Hisakazu Kotani; Junko Matsushima; Michihiro Inoue (IEEE J. Solid State Circuits, 1988)

A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier. - Hisakazu Kotani; Hironori Akamatsu; Junko Matsushima; Shozo Okada; Tsuyoshi Shiragasawa; Takayoshi Yamada; Michihiro Inoue (IEEE J. Solid State Circuits, 1990)

A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers. - Hiroyuki Yamauchi; Toshiki Yabu; Takayoshi Yamada; Michihiro Inoue (IEEE J. Solid State Circuits, 1990)

A 64-Mb DRAM with meshed power line. - Toshio Yamada; Yoshiro Nakata; Junko Hasegawa; Noriaki Amano; Akinori Shibayama; Masaru Sasago; Naoto Matsuo; Toshiki Yabu; Susumu Matsumoto; Shozo Okada; Michihiro Inoue (IEEE J. Solid State Circuits, 1991)

A New Testing Acceleration Chip for Low-Cost Memory Tests. - Michihiro Inoue; Toshio Yamada; Atsushi Fujiwara (IEEE Des. Test Comput., 1993)

A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's. - Hiroyuki Yamauchi; Toshikazu Suzuki; Akihiro Sawada; Tohru Iwata; Toshiaki Tsuji; Masashi Agata; Takashi Taniguchi; Yoshinori Odake; Kazuyuki Sawada; Teruhito Ohnishi; Masanori Fukumoto; Tsutomu Fujita; et al. (IEEE J. Solid State Circuits, 1993)

Effect of Mobility on Communication Performance in Overloaded One-Dimensional Cellular Networks. - Michihiro Inoue; Noriaki Yoshiura; Yoshikuni Onozato (ICDCIT, 2005)

Packaging in minimal fab: An integrated semiconductor line from wafer process to packaging process. - Michihiro Inoue; Fumito Imura; Arami Saruwatari; Shiro Hara (ICICDT, 2016)