MMLRU Selection Function: An Output Selection Function on Adaptive Routing. - Michihiro Koibuchi; Akiya Jouraku; Akira Funahashi; Hideharu Amano (PDCS, 2001)

The impact of output selection function on adaptive routing. - Akira Funahashi; Michihiro Koibuchi; Akiya Jouraku; Hideharu Amano (CATA, 2001)

L-Turn Routing: An Adaptive Routing in Irregular Networks. - Michihiro Koibuchi; Akira Funahashi; Akiya Jouraku; Hideharu Amano (ICPP, 2001)

Routing Algorithms Based on 2D Turn Model for Irregular Networks. - Akiya Jouraku; Michihiro Koibuchi; Hideharu Amano; Akira Funahashi (ISPAN, 2002)

The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. - Michihiro Koibuchi; Akiya Jouraku; Hideharu Amano (PDPTA, 2002)

Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. - Michihiro Koibuchi; Konosuke Watanabe; Kenichi Kono; Akiya Jouraku; Hideharu Amano (CLUSTER, 2003)

Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. - Michihiro Koibuchi; Akiya Jouraku; Konosuke Watanabe; Hideharu Amano (ICPP, 2003)

Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. - Yutaka Yamada; Hideharu Amano; Michihiro Koibuchi; Akiya Jouraku; Kenichiro Anjo; Katsunobu Nishimura (EUC, 2004)

BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. - Kenichiro Anjo; Yutaka Yamada; Michihiro Koibuchi; Akiya Jouraku; Hideharu Amano (IPDPS, 2004)

VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. - Tomohiro Otsuka; Michihiro Koibuchi; Akiya Jouraku; Hideharu Amano (ICPP, 2005)

Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. - Hiroki Matsutani; Michihiro Koibuchi; Yutaka Yamada; Akiya Jouraku; Hideharu Amano (ICPP Workshops, 2005)

In-Order Packet Delivery in Interconnection Networks using Adaptive Routing. - Juan Carlos Martínez; José Flich; Antonio Robles; Pedro López 001; José Duato; Michihiro Koibuchi (IPDPS, 2005)

Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (PDPTA, 2005)

MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing. - Michihiro Koibuchi; Akiya Jouraku; Hideharu Amano (IEICE Trans. Inf. Syst., 2005)

Enforcing in-order packet delivery in system area networks with adaptive routing. - Michihiro Koibuchi; Juan Carlos Martínez; José Flich; Antonio Robles; Pedro López 001; José Duato (J. Parallel Distributed Comput., 2005)

Path selection algorithm: the strategy for designing deterministic routing from alternative paths. - Michihiro Koibuchi; Akiya Jouraku; Hideharu Amano (Parallel Comput., 2005)

Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster. - Michihiro Koibuchi; Konosuke Watanabe; Tomohiro Otsuka; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2005)

A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (PDCS, 2006)

A Parametric Study of Scalable Interconnects on FPGAs. - Daihan Wang; Hiroki Matsutani; Masato Yoshimi; Michihiro Koibuchi; Hideharu Amano (ERSA, 2006)

Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. - Tomohiro Otsuka; Michihiro Koibuchi; Tomohiro Kudoh; Hideharu Amano (ICPP, 2006)

Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ISPA, 2006)

A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. - Michihiro Koibuchi; Kenichiro Anjo; Yutaka Yamada; Akiya Jouraku; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2006)

A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. - Daihan Wang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (FPL, 2007)

Layer-1 Bandwidth on Demand Services in SINET3. - Shigeo Urushidani; Jun Matsukata; Kensuke Fukuda; Shunji Abe; Yusheng Ji; Michihiro Koibuchi; Shigeki Yamada; Kaori Shimizu; Tomonori Takeda; Ichiro Inoue; Kohei Shiomoto (GLOBECOM, 2007)

Investigating QoS Performance on a Testbed Network. - Jumpot Phuritatkul; Kien Nguyen 002; Michihiro Koibuchi; Yusheng Ji (ICCCN, 2007)

Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICPP, 2007)

Performance Improvement Methodology for ClearSpeed's CSX600. - Yuri Nishikawa; Michihiro Koibuchi; Masato Yoshimi; Kenichi Miura; Hideharu Amano (ICPP, 2007)

Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IPDPS, 2007)

Architectural Design of Next-Generation Science Information Network. - Shigeo Urushidani; Shunji Abe; Kensuke Fukuda; Jun Matsukata; Yusheng Ji; Michihiro Koibuchi; Shigeki Yamada (IEICE Trans. Commun., 2007)

A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. - Daihan Wang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2007)

An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks. - Akiya Jouraku; Michihiro Koibuchi; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2007)

Run-time power gating of on-chip routers using look-ahead routing. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Daihan Wang (ASP-DAC, 2008)

Impact of topology and link aggregation on a PC cluster with Ethernet. - Takafumi Watanabe; Masahiro Nakao; Tomoyuki Hiroyasu; Tomohiro Otsuka; Michihiro Koibuchi (CLUSTER, 2008)

A link removal methodology for Networks-on-Chip on reconfigurable systems. - Daihan Wang; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (FPL, 2008)

Three-Dimensional Layout of On-Chip Tree-Based Networks. - Hiroki Matsutani; Michihiro Koibuchi; D. Frank Hsu; Hideharu Amano (ISPAN, 2008)

A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. - Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano; Timothy Mark Pinkston (NOCS, 2008)

Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. - Hiroki Matsutani; Michihiro Koibuchi; Daihan Wang; Hideharu Amano (NOCS, 2008)

Prediction router: Yet another low latency on-chip router architecture. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tsutomu Yoshinaga (HPCA, 2009)

Implementation and Evaluation of Layer-1 Bandwidth-on-Demand Capabilities in SINET3. - Shigeo Urushidani; Kensuke Fukuda; Yusheng Ji; Michihiro Koibuchi; Shunji Abe; Motonori Nakamura; Shigeki Yamada; Kaori Shimizu; Rie Hayashi; Ichiro Inoue; Kohei Shiomoto (ICC, 2009)

Balanced Dimension-Order Routing for k-ary n-cubes. - José Miguel Montañana Aliaga; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano (ICPP Workshops, 2009)

An on/off link activation method for low-power ethernet in PC clusters. - Michihiro Koibuchi; Tomohiro Otsuka; Hiroki Matsutani; Hideharu Amano (IPDPS, 2009)

Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet Using Metaheuristics. - Tomoyuki Hiroyasu; Kozo Kawasaki; Michihiro Koibuchi; Shigeo Urushidani; Mitsunori Miki; Masato Yoshimi (ISDA, 2009)

Performance Analysis of ClearSpeed's CSX600 Interconnects. - Yuri Nishikawa; Michihiro Koibuchi; Masato Yoshimi; Akihiro Shitara; Kenichi Miura; Hideharu Amano (ISPA, 2009)

An On/Off Link Activation Method for Power Regulation in InfiniBand. - José Miguel Montañana Aliaga; Michihiro Koibuchi; Takafumi Watanabe; Tomoyuki Hiroyasu; Hiroki Matsutani; Hideharu Amano (PDPTA, 2009)

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. - Daihan Wang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2009)

Design of versatile academic infrastructure for multilayer network services. - Shigeo Urushidani; Shunji Abe; Yusheng Ji; Kensuke Fukuda; Michihiro Koibuchi; Motonori Nakamura; Shigeki Yamada; Kaori Shimizu; Rie Hayashi; Ichiro Inoue; Kohei Shiomoto (IEEE J. Sel. Areas Commun., 2009)

Impact of QoS operations on an experimental testbed network. - Jumpot Phuritatkul; Kien Nguyen 002; Michihiro Koibuchi; Yusheng Ji; Kensuke Fukuda; Shunji Abe; Jun Matsukata; Shigeo Urushidani; Shigeki Yamada (Simul. Model. Pract. Theory, 2009)

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. - Hiroki Matsutani; Michihiro Koibuchi; Yutaka Yamada; D. Frank Hsu; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2009)

An Efficient Path Setup for a Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Hiroki Matsutani; Michihiro Koibuchi; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (ICNC, 2010)

A Regular Expression Processor Embedded in Service-Friendly Router for Future Internet. - Yasutsugu Nagatomi; Michihiro Koibuchi; Hideyuki Kawashima; Koichi Inoue; Hiroaki Nishi (ICPP Workshops, 2010)

A variable-pipeline on-chip router optimized to traffic pattern. - Yuto Hirata; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (NoCArc@MICRO, 2010)

Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. - José Miguel Montañana Aliaga; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano (NAS, 2010)

A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. - Yuri Nishikawa; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano (NAS, 2010)

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. - Hiroki Matsutani; Michihiro Koibuchi; Daisuke Ikebuchi; Kimiyoshi Usami; Hiroshi Nakamura; Hideharu Amano (NOCS, 2010)

Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet. - Tomoaki Makino; Koichi Inoue; Michihiro Koibuchi; Hideyuki Kawashima; Hiroaki Nishi (PDPTA, 2010)

Dynamic Resource Allocation and QoS Control Capabilities of the Japanese Academic Backbone Network. - Shigeo Urushidani; Kensuke Fukuda; Michihiro Koibuchi; Motonori Nakamura; Shunji Abe; Yusheng Ji; Michihiro Aoki; Shigeki Yamada (Future Internet, 2010)

Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. - Hiroki Matsutani; Michihiro Koibuchi; Hiroshi Nakamura; Hideharu Amano (Low Power Networks-on-Chip, 2011)

Impact of Tohoku earthquake on R&E network in Japan. - Kensuke Fukuda; Michihiro Aoki; Shunji Abe; Yusheng Ji; Michihiro Koibuchi; Motonori Nakamura; Shigeki Yamada; Shigeo Urushidani (SWID@CoNEXT, 2011)

Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. - Michihiro Koibuchi; Takafumi Watanabe; Atsushi Minamihata; Masahiro Nakao; Tomoyuki Hiroyasu; Hiroki Matsutani; Hideharu Amano (ICNC, 2011)

A vertical bubble flow network using inductive-coupling for 3-D CMPs. - Hiroki Matsutani; Yasuhiro Take; Daisuke Sasaki; Masayuki Kimura; Yuki Ono; Yukinori Nishiyama; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (NOCS, 2011)

A Dynamic Link-Width Optimization for Network-on-Chip. - Daihan Wang; Michihiro Koibuchi; Tomohiro Yoneda; Hiroki Matsutani; Hideharu Amano (RTCSA (2), 2011)

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Hiroki Matsutani; Michihiro Koibuchi; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (Int. J. Netw. Comput., 2011)

An analytical network performance model for SIMD processor CSX600 interconnects. - Yuri Nishikawa; Michihiro Koibuchi; Masato Yoshimi; Kenichi Miura; Hideharu Amano (J. Syst. Archit., 2011)

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tsutomu Yoshinaga (IEEE Trans. Computers, 2011)

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. - Hiroki Matsutani; Michihiro Koibuchi; Daisuke Ikebuchi; Kimiyoshi Usami; Hiroshi Nakamura; Hideharu Amano (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet. - Michihiro Koibuchi; Tomohiro Otsuka; Tomohiro Kudoh; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2011)

3-D NoC on Inductive Wireless Interconnect. - Hiroki Matsutani; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (3D Integration for NoC-based SoC Architectures, 2011)

On incentive-based inter-domain caching for content delivery in future internet architectures. - Kalika Suksomboon; Yusheng Ji; Michihiro Koibuchi; Kensuke Fukuda; Shunji Abe; Motonori Nakamura; Michihiro Aoki; Shigeo Urushidani; Shigeki Yamada (AINTEC, 2012)

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. - Hiroki Matsutani; Yuto Hirata; Michihiro Koibuchi; Kimiyoshi Usami; Hiroshi Nakamura; Hideharu Amano (ASP-DAC, 2012)

A case for random shortcut topologies for HPC interconnects. - Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano; D. Frank Hsu; Henri Casanova (ISCA, 2012)

Throttling Control for Bufferless Routing in On-chip Networks. - Yicheng Guan; Cisse Ahmadou Dit Adi; Takefumi Miyoshi; Michihiro Koibuchi; Hidetsugu Irie; Tsutomu Yoshinaga (MCSoC, 2012)

Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. - Takeo Nakamura; Hiroki Matsutani; Michihiro Koibuchi; Kimiyoshi Usami; Hideharu Amano (MCSoC, 2012)

Cabinet Layout Optimization of Supercomputer Topologies for Shorter Cable Length. - Ikki Fujiwara; Michihiro Koibuchi; Henri Casanova (PDCAT, 2012)

A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms. - José Flich; Tor Skeie; Andres Mejia; Olav Lysne; Pedro López 001; Antonio Robles; José Duato; Michihiro Koibuchi; Tomas Rokicki; José Carlos Sancho (IEEE Trans. Parallel Distributed Syst., 2012)

A case for wireless 3D NoCs for CMPs. - Hiroki Matsutani; Paul Bogdan; Radu Marculescu; Yasuhiro Take; Daisuke Sasaki; Hao Zhang 020; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (ASP-DAC, 2013)

Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links. - Hao Zhang 020; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (COOL Chips, 2013)

Layout-conscious random topologies for HPC off-chip interconnects. - Michihiro Koibuchi; Ikki Fujiwara; Hiroki Matsutani; Henri Casanova (HPCA, 2013)

Future Low-Latency Networks for High Performance Computing. - Michihiro Koibuchi (CANDAR, 2013)

A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. - Daisuke Sasaki; Hao Zhang 020; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICA3PP (2), 2013)

Distributed Shortcut Networks: Layout-Aware Low-Degree Topologies Exploiting Small-World Effect. - Van K. Nguyen; Nhat T. X. Le; Ikki Fujiwara; Michihiro Koibuchi (ICPP, 2013)

PopCache: Cache more or less based on content popularity for information-centric networking. - Kalika Suksomboon; Saran Tarnoi; Yusheng Ji; Michihiro Koibuchi; Kensuke Fukuda; Shunji Abe; Motonori Nakamura; Michihiro Aoki; Shigeo Urushidani; Shigeki Yamada (LCN, 2013)

Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture. - Takahiro Kagami; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (NOCS, 2013)

A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation. - Cisse Ahmadou Dit Adi; Michihiro Koibuchi; Masato Yoshimi; Hidetsugu Irie; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2013)

Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). - Tomohiro Yoneda; José Flich Cardo; Jiang Xu 001; Michihiro Koibuchi (NII Shonan Meet. Rep., 2013)

Low-latency wireless 3D NoCs via randomized shortcut chips. - Hiroki Matsutani; Michihiro Koibuchi; Ikki Fujiwara; Takahiro Kagami; Yasuhiro Take; Tadahiro Kuroda; Paul Bogdan; Radu Marculescu; Hideharu Amano (DATE, 2014)

Darkfiber Planning for Extensible HPC Network Design under Uncertainties. - Fabien Chaix; Ikki Fujiwara; Michihiro Koibuchi (CANDAR, 2014)

Layout-aware expandable low-degree topology. - Nguyen T. Truong; Van K. Nguyen; Nhat T. X. Le; Ikki Fujiwara; Fabien Chaix; Michihiro Koibuchi (ICPADS, 2014)

Skywalk: A Topology for HPC Networks with Low-Delay Switches. - Ikki Fujiwara; Michihiro Koibuchi; Hiroki Matsutani; Henri Casanova (IPDPS, 2014)

Hierarchical Network Coding for Collective Communication on HPC Interconnects. - Ahmed Shalaby 001; Mohamed El-Sayed Ragab; Victor Goulart; Ikki Fujiwara; Michihiro Koibuchi (PDP, 2014)

Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. - Hao Zhang 020; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Extreme Big Data (EBD): Next Generation Big Data Infrastructure Technologies Towards Yottabyte/Year. - Satoshi Matsuoka; Hitoshi Sato; Osamu Tatebe; Michihiro Koibuchi; Ikki Fujiwara; Shuji Suzuki; Masanori Kakuta; Takashi Ishida 002; Yutaka Akiyama; Toyotaro Suzumura; Koji Ueno; Hiroki Kanezashi; et al. (Supercomput. Front. Innov., 2014)

3D NoC with Inductive-Coupling Links for Building-Block SiPs. - Yasuhiro Take; Hiroki Matsutani; Daisuke Sasaki; Michihiro Koibuchi; Tadahiro Kuroda; Hideharu Amano (IEEE Trans. Computers, 2014)

Highly available network design and resource management of SINET4. - Shigeo Urushidani; Michihiro Aoki; Kensuke Fukuda; Shunji Abe; Motonori Nakamura; Michihiro Koibuchi; Yusheng Ji; Shigeki Yamada (Telecommun. Syst., 2014)

A metamorphotic Network-on-Chip for various types of parallel applications. - Seiichi Tade; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (ASAP, 2015)

Augmenting low-latency HPC network with free-space optical links. - Ikki Fujiwara; Michihiro Koibuchi; Tomoya Ozaki; Hiroki Matsutani; Henri Casanova (HPCA, 2015)

Enabling Ideal Job Mapping on Wireless Supercomputers and Datacenters. - Yao Hu; Ikki Fujiwara; Michihiro Koibuchi (CANDAR, 2015)

Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. - Hiroshi Nakahara; Tomoya Ozaki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (MCSoC, 2015)

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. - Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura (NOCS, 2015)

Optimized Core-Links for Low-Latency NoCs. - Ryuta Kawano; Seiichi Tade; Ikki Fujiwara; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (PDP, 2015)

Singularity of Future Computer-System Networks. - Michihiro Koibuchi (SoICT, 2015)

The Case for Network Coding for Collective Communication on HPC Interconnection Networks. - Ahmed Shalaby 001; Ikki Fujiwara; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2015)

New Directions for a Japanese Academic Backbone Network. - Shigeo Urushidani; Shunji Abe; Kenjiro Yamanaka; Kento Aida; Shigetoshi Yokoyama; Hiroshi Yamada; Motonori Nakamura; Kensuke Fukuda; Michihiro Koibuchi; Shigeki Yamada (IEICE Trans. Inf. Syst., 2015)

Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects. - Ikki Fujiwara; Michihiro Koibuchi; Hiroki Matsutani; Henri Casanova (IEEE Trans. Parallel Distributed Syst., 2015)

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. - Ryuta Kawano; Hiroshi Nakahara; Seiichi Tade; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICIS, 2016)

HPC Job Mapping over Reconfigurable Wireless Links. - Yao Hu; Ikki Fujiwara; Michihiro Koibuchi (CCGrid, 2016)

LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. - Ryuta Kawano; Hiroshi Nakahara; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (CANDAR, 2016)

An Interconnection Network Exploiting Trade-Off between Routing Table Size and Path Length. - Thanh-Chung Kieu; Khanh-Van Nguyen; Nguyen T. Truong; Ikki Fujiwara; Michihiro Koibuchi (CANDAR, 2016)

Towards Ideal Hop Counts in Interconnection Networks with Arbitrary Size. - Michihiro Koibuchi; Ikki Fujiwara; Fabien Chaix; Henri Casanova (CANDAR, 2016)

Deterministic Construction of Regular Geometric Graphs with Short Average Distance and Limited Edge Length. - Satoshi Fujita; Koji Nakano; Michihiro Koibuchi; Ikki Fujiwara (ICA3PP, 2016)

Randomly Optimized Grid Graph for Low-Latency Interconnection Networks. - Koji Nakano; Daisuke Takafuji; Satoshi Fujita; Hiroki Matsutani; Ikki Fujiwara; Michihiro Koibuchi (ICPP, 2016)

A fully meshed backbone network for data-intensive sciences and SDN services. - Takashi Kurimoto; Shigeo Urushidani; Hiroshi Yamada; Kenjiro Yamanaka; Motonori Nakamura; Shunji Abe; Kensuke Fukuda; Michihiro Koibuchi; Yusheng Ji; Hiroki Takakura; Shigeki Yamada (ICUFN, 2016)

Suitability of the Random Topology for HPC Applications. - Fabien Chaix; Ikki Fujiwara; Michihiro Koibuchi (PDP, 2016)

Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. - Daichi Fujiki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (PDP, 2016)

A diagonal cabling approach to data center and HPC systems. - Truong Thao Nguyen; Ikki Fujiwara; Michihiro Koibuchi (SoICT, 2016)

Optical network technologies for HPC: computer-architects point of view. - Michihiro Koibuchi; Ikki Fujiwara; Kiyo Ishii; Shu Namiki; Fabien Chaix; Hiroki Matsutani; Hideharu Amano; Tomohiro Kudoh (IEICE Electron. Express, 2016)

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. - Akram Ben Ahmed; Hiroki Matsutani; Michihiro Koibuchi; Kimiyoshi Usami; Hideharu Amano (IEICE Trans. Electron., 2016)

Job Mapping and Scheduling on Free-Space Optical Networks. - Yao Hu; Ikki Fujiwara; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2016)

Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface. - Hiroshi Nakahara; Tomoya Ozaki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2016)

Layout-Conscious Expandable Topology for Low-Degree Interconnection Networks. - Truong Thao Nguyen; Khanh-Van Nguyen; Ikki Fujiwara; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2016)

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. - Takahiro Kagami; Hiroki Matsutani; Michihiro Koibuchi; Yasuhiro Take; Tadahiro Kuroda; Hideharu Amano (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Cable-geometric error-prone approach for low-latency interconnection networks. - Thao-Nguyen Nguyen; Michihiro Koibuchi (CCGrid, 2017)

A Case for Uni-directional Network Topologies in Large-Scale Clusters. - Michihiro Koibuchi; Tomohiro Totoki; Hiroki Matsutani; Hideharu Amano; Fabien Chaix; Ikki Fujiwara; Henri Casanova (CLUSTER, 2017)

In-switch approximate processing: Delayed tasks management for MapReduce applications. - Koya Mitsuzuka; Ami Hayashi; Michihiro Koibuchi; Hideharu Amano; Hiroki Matsutani (FPL, 2017)

High-Bandwidth Low-Latency Approximate Interconnection Networks. - Daichi Fujiki; Kiyo Ishii; Ikki Fujiwara; Hiroki Matsutani; Hideharu Amano; Henri Casanova; Michihiro Koibuchi (HPCA, 2017)

SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era. - Takashi Kurimoto; Shigeo Urushidani; Hiroshi Yamada; Kenjiro Yamanaka; Motonori Nakamura; Shunji Abe; Kensuke Fukuda; Michihiro Koibuchi; Hiroki Takakura; Shigeki Yamada; Yusheng Ji (ICC, 2017)

Towards Tightly-coupled Datacenter with Free-space Optical Links. - Yao Hu; Hiroaki Hara; Ikki Fujiwara; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (ICCBDC, 2017)

HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICPADS, 2017)

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. - Ryota Yasudo; Michihiro Koibuchi; Koji Nakano; Hiroki Matsutani; Hideharu Amano (ICPP, 2017)

3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. - Hiroshi Nakahara; Ryota Yasudo; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (ISPAN-FCST-ISCC, 2017)

A Case of Electrical Circuit Switched Interconnection Network for Parallel Computers. - Yao Hu; Tomohiro Kudoh; Michihiro Koibuchi (PDCAT, 2017)

A Layout-Oriented Routing Method for Low-Latency HPC Networks. - Ryuta Kawano; Hiroshi Nakahara; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2017)

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. - Ryuta Kawano; Hiroshi Nakahara; Seiichi Tade; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2017)

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. - Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura (IEEE Trans. Computers, 2017)

Distributed Shortcut Networks: Low-Latency Low-Degree Non-Random Topologies Targeting the Diameter and Cable Length Trade-Off. - Nguyen T. Truong; Ikki Fujiwara; Michihiro Koibuchi; Khanh-Van Nguyen (IEEE Trans. Parallel Distributed Syst., 2017)

Performance Evaluation of Collective Communication on Random Network Topology. - Ke Cui; Michihiro Koibuchi (CANDAR Workshops, 2018)

The Impact of Job Mapping on Random Network Topology. - Yao Hu; Michihiro Koibuchi (CANDAR Workshops, 2018)

An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. - Naoya Niwa; Tomohiro Totoki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (CANDAR Workshops, 2018)

An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking. - Tomohiro Totoki; Michihiro Koibuchi; Hideharu Amano (CANDAR Workshops, 2018)

Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. - Akram Ben Ahmed; Hayate Okuhara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (MCSoC, 2018)

Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications. - Truong Thao Nguyen; Hiroki Matsutani; Michihiro Koibuchi (NCA, 2018)

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. - Akram Ben Ahmed; Daichi Fujiki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (NOCS, 2018)

Enhancing Job Scheduling on Inter-Rackscale Datacenters with Free-Space Optical Links. - Yao Hu; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2018)

Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. - Koya Mitsuzuka; Michihiro Koibuchi; Hideharu Amano; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2018)

Sparse 3-D NoCs with Inductive Coupling. - Michihiro Koibuchi; Lambert T. Leong; Tomohiro Totoki; Naoya Niwa; Hiroki Matsutani; Hideharu Amano; Henri Casanova (DAC, 2019)

Diameter/ASPL-Based Mapping of Applications with Uncertain Communication over Random Interconnection Networks. - Yao Hu; Michihiro Koibuchi (ICPADS, 2019)

The Case for Water-Immersion Computer Boards. - Michihiro Koibuchi; Ikki Fujiwara; Naoya Niwa; Tomohiro Totoki; Shoichi Hirasawa (ICPP, 2019)

The Impact of Application Mapping on Non-Random and Random Network Topologies. - Yao Hu; Michihiro Koibuchi (ISPA/BDCloud/SocialCom/SustainCom, 2019)

A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. - Keita Azegami; Kazusa Musha; Kazuei Hironaka; Akram Ben Ahmed; Michihiro Koibuchi; Yao Hu; Hideharu Amano (MCSoC, 2019)

Low-Latency Error-Prone Optical Networks for Fast Approximate Computation on High-End Datacenters. - Michihiro Koibuchi (OECC/PSC, 2019)

Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems. - Yao Hu; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2019)

Foreword. - Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2019)

Designing High-Performance Interconnection Networks with Host-Switch Graphs. - Ryota Yasudo; Michihiro Koibuchi; Koji Nakano; Hiroki Matsutani; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2019)

Dual-Plane Isomorphic Hypercube Network. - Takeo Hosomi; Ryota Yasudo; Michihiro Koibuchi; Shinji Shimojo (HPC Asia, 2020)

A Diagonal Checksum Algorithm-Based Fault Tolerance for Parallel Matrix Multiplication. - Ke Cui; Michihiro Koibuchi (CANDAR (Workshops), 2020)

Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. - Kohei Ito; Kensuke Iizuka; Kazuei Hironaka; Yao Hu; Michihiro Koibuchi; Hideharu Amano (CANDAR (Workshops), 2020)

Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. - Tomoya Itsubo; Michihiro Koibuchi; Hideharu Amano; Hiroki Matsutani (PDP, 2020)

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2020)

Efficient Two-Opt Collective-Communication Operations on Low-Latency Random Network Topologies. - Ke Cui; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2020)

Application Mapping and Scheduling of Uncertain Communication Patterns onto Non-Random and Random Network Topologies. - Yao Hu; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2020)

Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2020)

GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. - Ryuta Kawano; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ACIT, 2021)

Packet Forwarding Cache of Commodity Switches for Parallel Computers. - Shoichi Hirasawa; Hayato Yamaki; Michihiro Koibuchi (CLUSTER, 2021)

Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression. - Naoya Niwa; Hideharu Amano; Michihiro Koibuchi (CANDAR, 2021)

The Case for Disjoint Job Mapping on High-Radix Networked Parallel Computers. - Yao Hu; Michihiro Koibuchi (ICA3PP (2), 2021)

Accelerating MPI Communication Using Floating-point Compression on Lossy Interconnection Networks. - Yao Hu; Michihiro Koibuchi (LCN, 2021)

Accelerating Parallel Sort on Tightly-Coupled FPGAs enabled by Onboard Si-Photonics Transceivers. - Kenji Mizutani; Hiroshi Yamaguchi; Yutaka Urino; Michihiro Koibuchi (OFC, 2021)

A Case for Low-Latency Network-on-Chip using Compression Routers. - Naoya Niwa; Yoshiya Shikama; Hideharu Amano; Michihiro Koibuchi (PDP, 2021)

Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. - Yoshiya Shikama; Ryuta Kawano; Hiroki Matsutani; Hideharu Amano; Yusuke Nagasaka; Naoto Fukumoto; Michihiro Koibuchi (PDP, 2021)

Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. - Kohei Ito; Kensuke Iizuka; Kazuei Hironaka; Yao Hu; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2021)

An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. - Tomoya Itsubo; Michihiro Koibuchi; Hideharu Amano; Hiroki Matsutani (IEICE Trans. Inf. Syst., 2021)

OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives. - Kenji Mizutani; Hiroshi Yamaguchi; Yutaka Urino; Michihiro Koibuchi (IEEE Trans. Computers, 2021)

A Scalable Distributed Radix Sorter for FPGA Clusters using High-Bandwidth Memory Networks. - Yutaka Urino; Takanori Shimizu; Hiroshi Yamaguchi; Kenji Mizutani; Shigeru Nakamura; Tatsuya Usuki; Michihiro Koibuchi (FCCM, 2022)

Message from the Organizers: CANDAR 2022. - Jacir Luiz Bordim; Michihiro Koibuchi; Satoshi Fujita; Koji Nakano (CANDAR, 2022)

Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. - Ryuta Kawano; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (CANDAR, 2022)

Scalable Low-Latency Inter-FPGA Networks. - Kien Trung Pham; Truong Thao Nguyen; Hiroshi Yamaguchi; Yutaka Urino; Michihiro Koibuchi (IPDPS, 2022)

A High-Radix Circulant Network Topology for Efficient Collective Communication. - Ke Cui; Michihiro Koibuchi (PDCAT, 2022)

A Hardware Trojan Exploiting Coherence Protocol on NoCs. - Yoshiya Shikama; Michihiro Koibuchi; Hideharu Amano (PDCAT, 2022)

Accelerating parallel data processing using optically tightly coupled FPGAs. - Kenji Mizutani; Hiroshi Yamaguchi; Yutaka Urino; Michihiro Koibuchi (JOCN, 2022)

A traffic-aware memory-cube network using bypassing. - Yoshiya Shikama; Ryuta Kawano; Hiroki Matsutani; Hideharu Amano; Yusuke Nagasaka; Naoto Fukumoto; Michihiro Koibuchi (Microprocess. Microsystems, 2022)

Boosting the Performance of Interconnection Networks by Selective Data Compression. - Naoya Niwa; Hideharu Amano; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2022)

Performance Improvement of Federated Learning Server using Smart NIC. - Naoki Shibahara; Michihiro Koibuchi; Hiroki Matsutani (CANDARW, 2023)

An Auto-Tuning Method for High-Bandwidth Low-Latency Approximate Interconnection Networks. - Shoichi Hirasawa; Michihiro Koibuchi (PDP, 2023)

Experimental Demonstration of Approximate Communication Based on Radio-Over- Fiber Systems. - Toshiki Ishimaru; Takatomo Mihana; Michihiro Koibuchi; Tetsuya Kawanishi; Makoto Naruse (IEEE Access, 2023)

Designing low-diameter interconnection networks with multi-ported host-switch graphs. - Ryota Yasudo; Koji Nakano; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano (Concurr. Comput. Pract. Exp., 2023)

A Case for Offloading Federated Learning Server on Smart NIC. - Naoki Shibahara; Michihiro Koibuchi; Hiroki Matsutani (CoRR, 2023)

A Compression Router for Low-Latency Network-on-Chip. - Naoya Niwa; Yoshiya Shikama; Hideharu Amano; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2023)

Effective switchless inter-FPGA memory networks. - Truong Thao Nguyen; Kien Trung Pham; Hiroshi Yamaguchi; Yutaka Urino; Michihiro Koibuchi (J. Parallel Distributed Comput., 2023)

A Bandwidth-Optimal All-to-All Communication in Two-Dimensional Fully Connected Network. - Kien Trung Pham; Truong Thao Nguyen; Michihiro Koibuchi (CCGrid, 2024)

The Case for Coherence Directories in Memory Cubes. - Yuki Kameyama; Naoya Niwa; Daichi Fujiki; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (MCSoC, 2024)

Performance of Radix Sort using All-to-all Optical Interconnection Network in an Eight-FPGA Cluster. - Kenji Mizutani; Yutaka Urino; Takanori Shimizu; Hiroshi Yamaguchi; Shigeru Nakamura; Tatsuya Usuki; Kiyo Ishii; Ryosuke Matsumoto; Takashi Inoue; Shu Namiki; Michihiro Koibuchi (OFC, 2024)

Lossy Compressed Collective Inter-FPGA Communications. - Michihiro Koibuchi; Yoshinobu Ishida; Shoichi Hirasawa; Yao Hu; Takumi Honda; Yusuke Nagasaka; Naoto Fukumoto (HPC Asia, 2025)

In-network stable radix sorter using many FPGAs with high-bandwidth photonics [Invited]. - Kenji Mizutani; Yutaka Urino; Takanori Shimizu; Hiroshi Yamaguchi; Shigeru Nakamura; Tatsuya Usuki; Kiyo Ishii; Ryosuke Matsumoto; Takashi Inoue; Shu Namiki; Michihiro Koibuchi (J. Opt. Commun. Netw., 2025)