Test Response Compression Based on Huffman Coding. - Hideyuki Ichihara; Michihiro Shintani; Toshihiro Ohara; Tomoo Inoue (Asian Test Symposium, 2003)

A Test Decompression Scheme for Variable-Length Coding. - Hideyuki Ichihara; Masakuni Ochi; Michihiro Shintani; Tomoo Inoue (Asian Test Symposium, 2004)

A Huffman-based coding with efficient test application. - Michihiro Shintani; Toshihiro Ohara; Hideyuki Ichihara; Tomoo Inoue (ASP-DAC, 2005)

Huffman-Based Test Response Coding. - Hideyuki Ichihara; Michihiro Shintani; Tomoo Inoue (IEICE Trans. Inf. Syst., 2005)

An Adaptive Decompressor for Test Application with Variable-Length Coding. - Hideyuki Ichihara; Masakuni Ochi; Michihiro Shintani; Tomoo Inoue (Inf. Media Technol., 2006)

A Variable-Length Coding Adjustable for Compressed Test Application. - Hideyuki Ichihara; Toshihiro Ohara; Michihiro Shintani; Tomoo Inoue (IEICE Trans. Inf. Syst., 2007)

An Adaptive Test for Parametric Faults Based on Statistical Timing Information. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Hiroyuki Ueyama; Takashi Sato 001; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu (Asian Test Symposium, 2009)

Small Delay Fault Model for Intra-Gate Resistive Open Defects. - Masayuki Arai; Akifumi Suto; Kazuhiko Iwasaki; Katsuyuki Nakano; Michihiro Shintani; Kazumi Hatayama; Takashi Aikyo (VTS, 2009)

Scan based process parameter estimation through path-delay inequalities. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (ISCAS, 2010)

Path clustering for adaptive test. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (VTS, 2010)

A Bayesian-based process parameter estimation using IDDQ current signature. - Michihiro Shintani; Takashi Sato 001 (VTS, 2012)

An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. - Michihiro Shintani; Takashi Sato 001 (ASP-DAC, 2013)

Device-Parameter Estimation through IDDQ Signatures. - Michihiro Shintani; Takashi Sato 001 (IEICE Trans. Inf. Syst., 2013)

Sensorless estimation of global device-parameters based on Fmax testing. - Michihiro Shintani; Takashi Sato 001 (ICCAD, 2014)

IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination. - Michihiro Shintani; Takashi Sato 001 (IEICE Trans. Inf. Syst., 2014)

A Variability-Aware Adaptive Test Flow for Test Quality Improvement. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. - Song Bian 001; Michihiro Shintani; Zheng Wang 020; Masayuki Hiromoto; Anupam Chattopadhyay; Takashi Sato 001 (ATS, 2016)

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. - Song Bian 001; Michihiro Shintani; Shumpei Morita; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ACM Great Lakes Symposium on VLSI, 2016)

Nonlinear delay-table approach for full-chip NBTI degradation prediction. - Song Bian 001; Michihiro Shintani; Shumpei Morita; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2016)

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. - Michihiro Shintani; Takumi Uezono; Kazumi Hatayama; Kazuya Masu; Takashi Sato 001 (J. Electron. Test., 2016)

Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. - Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. - Yu-Guang Chen; Michihiro Shintani; Takashi Sato 001; Yiyu Shi 001; Shih-Chieh Chang (ASP-DAC, 2017)

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. - Fakir Sharif Hossain; Tomokazu Yoneda; Michihiro Shintani; Michiko Inoue; Alex Orailoglu (ATS, 2017)

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. - Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (DAC, 2017)

Comparative study of path selection and objective function in replacing NBTI mitigation logic. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2017)

Identification and Application of Invariant Critical Paths under NBTI Degradation. - Song Bian 001; Shumpei Morita; Michihiro Shintani; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Decimal Multiplication Using Combination of Software and Hardware. - Mian Riaz-ul-haque; Michihiro Shintani; Michiko Inoue (APCCAS, 2018)

Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ASP-DAC, 2018)

Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage. - Mamoru Ishizaka; Michihiro Shintani; Michiko Inoue (ATS, 2018)

A study on NBTI-induced delay degradation considering stress frequency dependence. - Zuitoku Shin; Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2018)

Variation-Aware Hardware Trojan Detection through Power Side-channel. - Fakir Sharif Hossain; Michihiro Shintani; Michiko Inoue; Alex Orailoglu (ITC, 2018)

Artificial Neural Network Based Test Escape Screening Using Generative Model. - Michihiro Shintani; Michiko Inoue; Yoshiyuki Nakamura (ITC, 2018)

Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling. - Foisal Ahmed; Michihiro Shintani; Michiko Inoue (ETS, 2019)

Low Cost Recycled FPGA Detection Using Virtual Probe Technique. - Foisal Ahmed; Michihiro Shintani; Michiko Inoue (ITC-Asia, 2019)

Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. - Riaz-ul-haque Mian; Michihiro Shintani; Michiko Inoue (SoCC, 2019)

Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs. - Yohei Nakamura; Naotaka Kuroda; Atsushi Yamaguchi; Ken Nakahara; Michihiro Shintani; Takashi Sato 001 (ATS, 2020)

LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement. - Michihiro Shintani; Tomoki Mino; Michiko Inoue (ATS, 2020)

Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation. - Aoi Ueda; Michihiro Shintani; Michiko Inoue; Takashi Sato 001 (ATS, 2020)

Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit. - Mamoru Ishizaka; Michihiro Shintani; Michiko Inoue (J. Electron. Test., 2020)

Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework. - Foisal Ahmed; Michihiro Shintani; Michiko Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network. - Michihiro Shintani; Mamoru Ishizaka; Michiko Inoue (ATS, 2021)

Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation. - Yuya Isaka; Foisal Ahmed; Michihiro Shintani; Michiko Inoue (IOLTS, 2021)

Study on High-Accuracy and Low-Cost Recycled FPGA Detection. - Foisal Ahmed; Michihiro Shintani; Michiko Inoue (ITC, 2021)

Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. - Michihiro Shintani; Riaz-ul-haque Mian; Michiko Inoue; Tomoki Nakamura; Masuo Kajiyama; Makoto Eiki (ITC, 2021)

Hardware-Software Co-Design for Decimal Multiplication. - Riaz-ul-haque Mian; Michihiro Shintani; Michiko Inoue (Comput., 2021)

Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation. - Michihiro Shintani; Aoi Ueda; Takashi Sato 001 (CoRR, 2021)

Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling. - Foisal Ahmed; Michihiro Shintani; Michiko Inoue (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data. - Makoto Eiki; Tomoki Nakamura; Masuo Kajiyama; Michiko Inoue; Michihiro Shintani (ITC, 2022)

Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression. - Kyohei Shimozato; Michihiro Shintani; Takashi Sato 001 (CoRR, 2022)

Systematic Unsupervised Recycled Field-Programmable Gate Array Detection. - Yuya Isaka; Michihiro Shintani; Foisal Ahmed; Michiko Inoue (CoRR, 2022)

Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Feasibility Study of Incremental Neural Network Based Test Escape Detection by Introducing Transfer Learning Technique. - Ayano Takaya; Michihiro Shintani (ITC-Asia, 2023)

Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning. - Makoto Eiki; Tomoki Nakamura; Masuo Kajiyama; Michiko Inoue; Takashi Sato 001; Michihiro Shintani (ITC, 2023)

EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-Processing. - Yuya Isaka; Nau Sakaguchi; Michiko Inoue; Michihiro Shintani (DATE, 2024)

Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process. - Yuta Shintani; Michiko Inoue; Michihiro Shintani (DATE, 2024)

(Invited) Redefining Outliers for On-Wafer Electrical Testing. - Michihiro Shintani; Takashi Sato 001 (MLCAD, 2024)

Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits. - Ryosuke Matsuo; Kazuhisa Ogawa; Hidehisa Shiorni; Makoto Negoro; Ryutaco Ohira; Takefumi Miyoshi; Michihiro Shintani; Hiromitsu Awano; Takashi Sato 001; Jun Shiomi (QCE, 2024)

Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing. - Riaz-ul-haque Mian; Tomoki Nakamura; Masuo Kajiyama; Makoto Eiki; Michihiro Shintani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects. - Takuma Nagao; Tomoki Nakamura; Masuo Kajiyama; Makoto Eiki; Michiko Inoue; Michihiro Shintani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Hardware Trojan Detection by Fine-grained Power Domain Partitioning. - Takahiro Ishikawa; Kose Yokooji; Yoshihiro Midoh; Noriyuki Miura; Michihiro Shintani; Jun Shiomi (ASP-DAC, 2025)

Cryo-Compact Modeling Based on Sparse Gaussian Process. - Tetsuro Iwasaki; Takashi Sato 001; Michihiro Shintani (ASP-DAC, 2025)

Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. - Dondee Navarro; Shin Taniguchi; Chika Tanaka; Kazutoshi Kobayashi; Takashi Sato 001; Michihiro Shintani (ASP-DAC, 2025)

Cryo-HT: Hardware Trojan Activated at Cryogenic Temperatures. - Ayano Takaya; Ryuichi Nakajima; Jun Shiomi; Michihiro Shintani (ASP-DAC, 2025)