Test Pattern Considerations for Fault Tolerant High Density DRAM. - Hiroshi Miyamoto; Koichiro Mashiko; Yoshikazu Morooka; Kazutami Arimoto; Michihiro Yamada; Takao Nakano (ITC, 1985)

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. - Kazutami Arimoto; Kazuyasu Fujishima; Yoshio Matsuda; Masaki Tsukude; Tukasa Oishi; Wataru Wakamiya; Shin'ichi Satoh 004; Michihiro Yamada; Takao Nakano (IEEE J. Solid State Circuits, 1989)

Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM. - Hiroshi Miyamoto; Tadato Yamagata; Shigeru Mori; Tetsuya Aono; Ikuo Ogoh; Michihiro Yamada (IEEE J. Solid State Circuits, 1990)

An Address Maskable Parallel Testing for Ultra High Density DRAMs. - Yoshikazu Morooka; Shigeru Mori; Hiroshi Miyamoto; Michihiro Yamada (ITC, 1991)

Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond. - Shigeru Kikuda; Hiroshi Miyamoto; Shigeru Mori; Mitsutaka Niiro; Michihiro Yamada (IEEE J. Solid State Circuits, 1991)

A 45-ns 64-Mb DRAM with a merged match-line test architecture. - Shigeru Mori; Hiroshi Miyamoto; Yoshikazu Morooka; Shigeru Kikuda; Makoto Suwa; Mitsuya Kinoshita; Atsushi Hachisuka; Hideaki Arima; Michihiro Yamada; Tsutomu Yoshihara; Shimpei Kayano (IEEE J. Solid State Circuits, 1991)

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure. - Tadato Yamagata; Masaaki Mihara; Takeshi Hamamoto; Yasumitsu Murai; Toshifumi Kobayashi; Michihiro Yamada; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1992)

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. - Takahiro Tsuruda; Mako Kobayashi; Masaki Tsukude; Tadato Yamagata; Kazutami Arimoto; Michihiro Yamada (IEEE J. Solid State Circuits, 1997)

400-MHz random column operating SDRAM techniques with self-skew compensation. - Takeshi Hamamoto; Masaki Tsukude; Kazutami Arimoto; Yasuhiro Konishi; Takayuki Miyamoto; Hideyuki Ozaki; Michihiro Yamada (IEEE J. Solid State Circuits, 1998)

A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. - Hirotoshi Sato; Hideaki Nagaoka; Hiroaki Honda; Yukio Maki; Tomohisa Wada; Yutaka Arita; Kazuhito Tsutsumi; Makoto Taniguchi; Michihiro Yamada (IEEE J. Solid State Circuits, 1998)

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. - Yasunobu Nakase; Yoshikazu Morooka; David J. Perlman; Daniel J. Kolor; Jae-Myoung Choi; Hyun J. Shin; Tsutomu Yoshimura; Naoya Watanabe; Yoshio Matsuda; Masaki Kumanoya; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)

A 5.3-GB/s embedded SDRAM core with slight-boost scheme. - Akira Yamazaki; Tadato Yamagata; Makoto Hatakenaka; Atsushi Miyanishi; Isao Hayashi; Shigeki Tomishima; Atsuo Mangyo; Yoshio Yukinari; Takashi Tatsumi; Masashi Matsumura; Kazutami Arimoto; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)

Design methodology of embedded DRAM with virtual-socket architecture. - Tadaaki Yamauchi; Mitsuya Kinoshita; Teruhiko Amano; Katsumi Dosaka; Kazutami Arimoto; Hideyuki Ozaki; Michihiro Yamada; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2001)

Sharing or Non-sharing Credentials: A Study of What Motivates People to Be Malicious Insiders. - Koichi Niihara; Michihiro Yamada; Hiroaki Kikuchi (HCI (22), 2017)

Decision Tree Analysis on Environmental Factors of Insider Threats. - Michihiro Yamada; Koichi Niihara; Hiroaki Kikuchi (HCI (30), 2017)

How Much is Risk Increased by Sharing Credential in Group? - Hiroaki Kikuchi; Koichi Niihara; Michihiro Yamada (STM, 2017)

Evaluation and Development of Onomatopoeia CAPTCHAs. - Michihiro Yamada; Riko Shigeno; Hiroaki Kikuchi; Maki Sakamoto (PST, 2018)

Mathematical Model to Estimate Loss by Cyber Incident in Japan. - Michihiro Yamada; Hiroaki Kikuchi; Naoki Matsuyama; Koji Inui (ICISSP, 2019)

Development of a Cyber Incident Information Crawler. - Kazuki Ikegami; Michihiro Yamada; Hiroaki Kikuchi; Koji Inui (IMIS, 2019)

Best Security Measures to Reduce Cyber-Incident and Data Breach Risks. - Hiroaki Kikuchi; Michihiro Yamada; Kazuki Ikegami; Koji Inui (DPM/CBT@ESORICS, 2021)