A parallel sequential test generation system DESCARTES based on real-valued logic simulation. - Hiroshi Date; Michinobu Nakao; Kazumi Hatayama (Asian Test Symposium, 1995)

Accelerated Test Points Selection Method for Scan-Based BIST. - Michinobu Nakao; Kazumi Hatayama; Isao Higashi (Asian Test Symposium, 1997)

Low overhead test point insertion for scan-based BIST. - Michinobu Nakao; Seiji Kobayashi; Kazumi Hatayama; Kazuhiko Iijima; Seiji Terada (ITC, 1999)

A BIST approach for very deep sub-micron (VDSM) defects. - Yasuo Sato; Toyohito Ikeya; Michinobu Nakao; Takaharu Nagumo (ITC, 2000)

Test Generation for Multiple-Threshold Gate-Delay Fault Model. - Michinobu Nakao; Yoshikazu Kiyoshige; Kazumi Hatayama; Yasuo Sato; Takaharu Nagumo (Asian Test Symposium, 2001)

At-Speed Built-in Test for Logic Circuits with Multiple Clocks. - Kazumi Hatayama; Michinobu Nakao; Yasuo Sato (Asian Test Symposium, 2002)

Application of High-Quality Built-In Test to Industrial Designs. - Kazumi Hatayama; Michinobu Nakao; Yoshikazu Kiyoshige; Koichiro Natsume; Yasuo Sato; Takaharu Nagumo (ITC, 2002)

Enhancing Transition Fault Model for Delay Defect Diagnosis. - Wu-Tung Cheng; Brady Benware; Ruifeng Guo; Kun-Han Tsai; Takeo Kobayashi; Kazuyuki Maruo; Michinobu Nakao; Yoshiaki Fukui; Hideyuki Otake (ATS, 2008)

Hardware Overhead Reduction for Memory BIST. - Masayuki Arai; Kazuhiko Iwasaki; Michinobu Nakao; Iwao Suzuki (ITC, 2008)

Reduction of Area per Good Die for SoC Memory Built-In Self-Test. - Masayuki Arai; Tatsuro Endo; Kazuhiko Iwasaki; Michinobu Nakao; Iwao Suzuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs. - Chizu Matsumoto; Yuichi Hamamura; Michinobu Nakao; Kaname Yamasaki; Yoshikazu Saito; Shun'ichi Kaneko (IEICE Trans. Electron., 2013)