A 10 b 50 MHz pipelined CMOS A/D converter with S/H. - Michio Yotsuyanagi; Toshiyuki Etoh; Kazumi Hirata (IEEE J. Solid State Circuits, 1993)

A 2 V, 10 b, 20 Msample/s, mixed-mode subranging CMOS A/D converter. - Michio Yotsuyanagi; Hiroshi Hasegawa; Motoi Yamaguchi; Masaki Ishida; Kazuya Sone (IEEE J. Solid State Circuits, 1995)

A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture. - Muneo Fukaishi; Kazuyuki Nakamura; Masaharu Sato; Yutaka Tsutsui; Syuji Kishi; Michio Yotsuyanagi (IEEE J. Solid State Circuits, 1998)

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications. - Muneo Fukaishi; Satoshi Nakamura; Akio Tajima; Yasushi Kinoshita; Yoshihiko Suemura; Hisamitsu Suzuki; Toshiro Itani; Hidenobu Miyamoto; Naoya Henmi; Tohru Yamazaki; Michio Yotsuyanagi (IEEE J. Solid State Circuits, 1999)

A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays. - Muneo Fukaishi; Kazuyuki Nakamura; Hideki Heiuchi; Yoshinori Hirota; Yoetsu Nakazawa; Hidenori Ikeno; Hiroshi Hayama; Michio Yotsuyanagi (IEEE J. Solid State Circuits, 2000)

Low-Voltage Operational Active Inductor for LNA Circuit. - Masaaki Soda; Ningyi Wang; Michio Yotsuyanagi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture. - Yuji Nakajima; Akemi Sakaguchi; Toshio Ohkido; Norihito Kato; Tetsuya Matsumoto; Michio Yotsuyanagi (IEEE J. Solid State Circuits, 2010)

A 7b 1.4GS/s ADC with offset drift suppression techniques for one-time calibration. - Yuji Nakajima; Norihito Kato; Akemi Sakaguchi; Toshio Ohkido; Kenji Shimomaki; Hiroko Masuda; Chikahiro Shiroma; Michio Yotsuyanagi; Takahiro Miki (CICC, 2012)