Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. - Tatsuo Higuchi 001; Michitaka Kameyama (IEEE Trans. Computers, 1977)

Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module. - Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE Trans. Computers, 1977)

Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits. - Nobuhiro Tomabechi; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1986)

Design of low-power quaternary CMOS logic circuits. - Chotei Zukeran; Chushin Afuso; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1986)

Design and implementation of an nmos image processor based on quaternary logic. - Takahiro Hanyu; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1987)

Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic. - Shoji Kawahito; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1987)

Design of micropower CMOS quaternary memory circuits. - Chotei Zukeran; Chushin Afuso; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1987)

A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. - Michitaka Kameyama; Shoji Kawahito; Tatsuo Higuchi 001 (Computer, 1988)

Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation. - Xi Yue Huang; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1988)

Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System. - Michitaka Kameyama; Li Zheng; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1988)

A 32*32-bit multiplier using multiple-valued MOS current-mode circuits. - Shoji Kawahito; Michitaka Kameyama; Tatsuo Higuchi 001; Haruyasu Yamada (IEEE J. Solid State Circuits, 1988)

Implementation of a high performance LSI for inverse kinematics computation. - Michitaka Kameyama; Takao Matsumoto; Hideki Egami; Tatsuo Higuchi 001 (ICRA, 1989)

VLSI Computer for Robotics. - Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1989)

Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation. - Michitaka Kameyama; Shoji Kawahito; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1989)

Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic. - Michitaka Kameyama; Tsutomu Sekibe; Tatsuo Higuchi 001 (IEEE J. Solid State Circuits, 1989)

Toward the Age of Beyond-Binary Electronics and Systems. - Michitaka Kameyama (ISMVL, 1990)

Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. - Michitaka Kameyama; Masahiro Nomura; Tatsuo Higuchi 001 (ISMVL, 1990)

Robot Electronics System. - Tatsuo Higuchi 001; Michitaka Kameyama (J. Robotics Mechatronics, 1990)

Design of a Parallel Collision Detection Check VLSI Processor for Robot Manipulator. - Tadao Amada; Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1990)

Editorial: Computer Architecture for Robotics. - Michitaka Kameyama (J. Robotics Mechatronics, 1990)

Design of a Matrix Multiply-Addition VLSI Processor for Robot control. - Somchai Kittichaikoonkit; Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1990)

Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model. - Michitaka Kameyama; Takafumi Aoki; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1990)

Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits. - Michitaka Kameyama; Shugang Wei; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1990)

Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation. - Takeshi Kasuga; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1990)

Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems. - Shoji Kawahito; Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE J. Solid State Circuits, 1990)

High-Performance VLSI Processor for Robot Inverse Dynamics Computation. - Somchai Kittichaikoonkit; Michitaka Kameyama; Tatsuo Higuchi 001 (ICCD, 1991)

Design of Interconnection-Free Biomolecular Computing System. - Takafumi Aoki; Michitaka Kameyama; Tatsuo Higuchi 001 (ISMVL, 1991)

Design of a robust fault-tolerant multiplier. - Takeshi Kasuga; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1991)

Performance evaluation of a multivalued rsa encryption vlsi. - Shugang Wei; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1991)

Residue Arithmetic Based Multiple-Valued VLSI Image Processor. - Makoto Honda; Michitaka Kameyama; Tatsuo Higuchi 001 (ISMVL, 1992)

Design of a Multiple-Valued VLSI Processor for Digital Control. - Katsuhiko Shimabukuro; Michitaka Kameyama; Tatsuo Higuchi 001 (ISMVL, 1992)

Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. - Saneaki Tamaki; Michitaka Kameyama; Tatsuo Higuchi 001 (ISMVL, 1992)

Interconnection-Free Biomolecular Computing. - Takafumi Aoki; Michitaka Kameyama; Tatsuo Higuchi 001 (Computer, 1992)

Design of an ultrahigher-valued biocomputing system based on set-valued logic networks. - Takafumi Aoki; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1992)

Highly parallel collision detection processor for intelligent robots. - Michitaka Kameyama; Tadao Amada; Tatsuo Higuchi 001 (IEEE J. Solid State Circuits, 1992)

2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control. - Yoshichika Fujioka; Michitaka Kameyama (ICRA (3), 1993)

Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. - Masami Nakajima; Michitaka Kameyama (ISMVL, 1993)

Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations. - Shoui Kaqahito; Makoto Ishida; Tetsuro Nakamura; Kentaro Mizuno; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1993)

Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. - Takahiro Hanyu; Akira Mochizuki; Michitaka Kameyama (ISMVL, 1994)

Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations. - Masami Nakajima; Michitaka Kameyama (ISMVL, 1994)

Design of an Intelligent Fault-Tolerant System for Real-World Applications. - Shigeki Abe; Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1994)

Coordinate Transformation VLSI Processor for Redundant Manipulator Control. - Yoshichika Fujioka; Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1994)

Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles. - Masanori Hariyama; Michitaka Kameyama (J. Robotics Mechatronics, 1994)

Editorial: Intelligent Integrated Systems for Robotics. - Michitaka Kameyama (J. Robotics Mechatronics, 1994)

Next-Generation Intelligent Integrated Systems Based on Multiple-Valued Digital Processing. - Michitaka Kameyama (J. Robotics Mechatronics, 1994)

Latency Minimization of Parallel VLSI Processors for Robotics Using Integer Programming. - Bumchul Kim; Michitaka Kameyama (J. Robotics Mechatronics, 1994)

Design of a Model-Based Robot Vision VLSI Processor. - Yoshifumi Sasaki; Michitaka Kameyama (J. Robotics Mechatronics, 1994)

High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. - Shoji Kawahito; Makoto Ishida; Tetsuro Nakamura; Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE Trans. Computers, 1994)

Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. - Xiaowei Deng; Takahiro Hanyu; Michitaka Kameyama (ISMVL, 1995)

Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. - Takahiro Hanyu; Akira Mochizuki; Michitaka Kameyama (ISMVL, 1995)

Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. - M. Ryu; Michitaka Kameyama (ISMVL, 1995)

Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate. - Xiaowei Deng; Takahiro Hanyu; Michitaka Kameyama (IEICE Trans. Inf. Syst., 1995)

Digital Control Parallel VLSI Processor. - Michitaka Kameyama (J. Robotics Mechatronics, 1995)

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic. - Takahiro Hanyu; Michitaka Kameyama (IEEE J. Solid State Circuits, 1995)

Quaternary Universal-Literal CAM for Cellular Logic Image Processing. - Takahiro Hanyu; Manabu Arakaki; Michitaka Kameyama (ISMVL, 1996)

Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. - Masami Nakajima; Michitaka Kameyama (ISMVL, 1996)

Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects. - Masanori Hariyama; Yuichi Araumi; Michitaka Kameyama (J. Robotics Mechatronics, 1996)

Editorial: Integration of Intelligence for Robotics in VLSI Chips. - Michitaka Kameyama (J. Robotics Mechatronics, 1996)

Highly-Safe Intelligent Integrated Systems. - Michitaka Kameyama (J. Robotics Mechatronics, 1996)

VLSI Processor System for Robotics. - Michitaka Kameyama; Yoshichika Fujioka (J. Robotics Mechatronics, 1996)

Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure. - Michitaka Kameyama; Masayuki Sasaki (J. Robotics Mechatronics, 1996)

Design of a one-transistor-cell multiple-valued CAM. - Takahiro Hanyu; N. Kanagawa; Michitaka Kameyama (IEEE J. Solid State Circuits, 1996)

Design of a one-transistor-cell multiple-valued CAM. - Takahiro Hanyu; Naoki Kanagawa; Michitaka Kameyama (IEEE J. Solid State Circuits, 1996)

Author's Reply. - Shoji Kawahito; Makoto Ishida; Tasuro Nakamura; Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE Trans. Computers, 1996)

Low-power multiple-valued current-mode integrated circuit with current-source control and its application. - Takahiro Hanyu; Satoshi Kazama; Michitaka Kameyama (ASP-DAC, 1997)

One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. - Takahiro Hanyu; Manabu Arakaki; Michitaka Kameyama (ISMVL, 1997)

A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. - Masanori Hariyama; Yuichi Araumi; Michitaka Kameyama (Syst. Comput. Jpn., 1997)

Communication network protocol for real-time distributed control and its LSI implementation. - Koji Kobayashi; Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE Trans. Ind. Electron., 1997)

Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. - Masanori Hariyama; Michitaka Kameyama (ICRA, 1998)

Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. - Takahiro Hanyu; Takahiro Saito; Michitaka Kameyama (ISMVL, 1998)

Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. - Takahiro Hanyu; Kaname Teranishi; Michitaka Kameyama (ISMVL, 1998)

Design and evaluation of a digit-parallel multiple-valued content-addressable memory. - Takahiro Hanyu; Kaname Teranishi; Michitaka Kameyama (Syst. Comput. Jpn., 1998)

Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. - Takahiro Saito; Takahiro Hanyu; Michitaka Kameyama (Syst. Comput. Jpn., 1998)

Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. - Takahiro Hanyu; Tsukasa Ike; Michitaka Kameyama (ISMVL, 1999)

Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. - Takahiro Hanyu; Hiromitsu Kimura; Michitaka Kameyama (ISMVL, 1999)

Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture. - Yoshichika Fujioka; Michitaka Kameyama (Syst. Comput. Jpn., 1999)

Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. - Takahiro Hanyu; Tsukasa Ike; Michitaka Kameyama (ISMVL, 2000)

DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. - Takahiro Hanyu; Hiromitsu Kimura; Michitaka Kameyama (ISMVL, 2000)

Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. - Shunichi Kaeriyama; Takahiro Hanyu; Michitaka Kameyama (ISMVL, 2000)

Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. - Takahiro Hanyu; Tsukasa Ike; Michitaka Kameyama (PRDC, 2000)

Architecture of a high-performance stereo vision VLSI processor. - Masanori Hariyama; Seunghwan Lee; Michitaka Kameyama (Adv. Robotics, 2000)

Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture. - Masanori Hariyama; Michitaka Kameyama (J. Robotics Mechatronics, 2000)

Path Planning Based on Distance Transformation and Its VLSI Implementation. - Masanori Hariyama; Michitaka Kameyama (J. Robotics Mechatronics, 2000)

Editorial: Intelligent Integrated Systems for Human-Oriented Information Society. - Michitaka Kameyama (J. Robotics Mechatronics, 2000)

Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction. - Hideki Kazama; Masanori Hariyama; Michitaka Kameyama (J. Robotics Mechatronics, 2000)

VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. - Masanori Hariyama; Toshiki Takeuchi; Michitaka Kameyama (ICRA, 2001)

Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. - Takahiro Hanyu; Michitaka Kameyama; Katsuhiko Shimabukuro; Chotei Zukeran (ISMVL, 2001)

Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. - Tsukasa Ike; Takahiro Hanyu; Michitaka Kameyama (ISMVL, 2001)

Fully Source-Coupled Logic Based Multiple-Valued VLSI. - Tsukasa Ike; Takahiro Hanyu; Michitaka Kameyama (ISMVL, 2002)

Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. - Hiromitsu Kimura; Takahiro Hanyu; Michitaka Kameyama (ISMVL, 2002)

High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. - Naotaka Ohsawa; Masanori Hariyama; Michitaka Kameyama (ISVLSI, 2002)

Multiple-Valued Dynamic Source-Coupled Logic. - Takahiro Hanyu; Akira Mochizuki; Michitaka Kameyama (ISMVL, 2003)

Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. - Takahiro Hanyu; Tomohiro Takahashi; Michitaka Kameyama (ISMVL, 2003)

Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization. - Tsukasa Ike; Takahiro Hanyu; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2003)

Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications. - Hiromitsu Kimura; Takahiro Hanyu; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2003)

Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic. - Haque Mohammad Munirul; Michitaka Kameyama (ISMVL, 2004)

Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications. - Haque Mohammad Munirul; Michitaka Kameyama (ISMVL, 2004)

Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. - Weisheng Chong; Masanori Hariyama; Michitaka Kameyama (ISVLSI, 2004)

Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. - Naotaka Ohsawa; Osamu Sakamoto; Masanori Hariyama; Michitaka Kameyama (ISVLSI, 2004)

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI. - Hiromitsu Kimura; Takahiro Hanyu; Michitaka Kameyama; Yoshikazu Fujimori; Takashi Nakamura; Hidemi Takasu (IEEE J. Solid State Circuits, 2004)

Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. - Weisheng Chong; Sho Ogata; Masanori Hariyama; Michitaka Kameyama (IPDPS, 2005)

VLSI architecture based on packet data transfer scheme and its application. - Yuya Homma; Michitaka Kameyama; Yoshichika Fujioka; Nobuhiro Tomabechi (ISCAS (2), 2005)

Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer. - Tomoaki Hasegawa; Yuya Homma; Michitaka Kameyama (ISMVL, 2005)

Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic. - Haque Mohammad Munirul; Tomoaki Hasegawa; Michitaka Kameyama (ISMVL, 2005)

Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. - Masanori Hariyama; Weisheng Chong; Sho Ogata; Michitaka Kameyama (ISVLSI, 2005)

Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. - Weisheng Chong; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. - Masanori Hariyama; Yasuhiro Kobayashi; Haruka Sasaki; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. - Masanori Hariyama; Haruka Sasaki; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2005)

Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic. - Takahiro Hanyu; Shunichi Kaeriyama; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2005)

Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic. - Michitaka Kameyama; Takahiro Hanyu; Takafumi Aoki (J. Multiple Valued Log. Soft Comput., 2005)

Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic. - Akira Mochizuki; Takahiro Hanyu; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2005)

Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. - Masanori Hariyama; Tetsuya Aoyama; Michitaka Kameyama (IEEE Trans. Computers, 2005)

A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. - Masanori Hariyama; Michitaka Kameyama (APCCAS, 2006)

GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. - W. H. Muthumala; Masanori Hariyama; Michitaka Kameyama (APCCAS, 2006)

Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. - Yoshihiro Nakatani; Masanori Hariyama; Michitaka Kameyama (IPDPS, 2006)

Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture. - Haque Mohammad Munirul; Tomoaki Hasegawa; Michitaka Kameyama (ISMVL, 2006)

Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit. - Haque Mohammad Munirul; Michitaka Kameyama (ISMVL, 2006)

Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. - Yoshihiro Nakatani; Masanori Hariyama; Michitaka Kameyama (ISMVL, 2006)

Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. - Masanori Hariyama; Michitaka Kameyama; Yasuhiro Kobayashi (ISVLSI, 2006)

A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. - Masanori Hariyama; Sho Ogata; Michitaka Kameyama (IEICE Trans. Electron., 2006)

Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. - Masanori Hariyama; Shigeo Yamadera; Michitaka Kameyama (IEICE Trans. Electron., 2006)

Special Section on VLSI Technology toward Frontiers of New Market. - Michitaka Kameyama (IEICE Trans. Electron., 2007)

Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. - Tasuku Ito; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2007)

Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. - Nobuaki Okada; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2007)

Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. - Masanori Hariyama; Shota Ishihara; Noriaki Idobata; Michitaka Kameyama (ERSA, 2008)

Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (ERSA, 2008)

FPGA implementation of a vehicle detection algorithm using three-dimensional information. - Masanori Hariyama; Kensaku Yamashita; Michitaka Kameyama (IPDPS, 2008)

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. - Nobuaki Okada; Michitaka Kameyama (ISMVL, 2008)

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. - Masanori Hariyama; Shota Ishihara; Michitaka Kameyama (IEICE Trans. Electron., 2008)

Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. - Masanori Hariyama; Naoto Yokoyama; Michitaka Kameyama (IEICE Trans. Electron., 2008)

Memory Allocation for Multi-Resolution Image Processing. - Yasuhiro Kobayashi; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2008)

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation. - Nobuaki Okada; Michitaka Kameyama (IEICE Trans. Electron., 2008)

Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. - Hasitha Muthumala Waidyasooriya; Weisheng Chong; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2008)

Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. - Masanori Hariyama; Keita Tanji; Michitaka Kameyama (ERSA, 2009)

A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. - Shota Ishihara; Noriaki Idobata; Masanori Hariyama; Michitaka Kameyama (ERSA, 2009)

An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. - Shota Ishihara; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (ERSA, 2009)

Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (ERSA, 2009)

Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. - Wim J. C. Melis; Shuhei Chizuwa; Michitaka Kameyama (ISMVL, 2009)

Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. - Nobuaki Okada; Michitaka Kameyama (ISMVL, 2009)

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2009)

Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. - Yasuhiro Kobayashi; Masanori Hariyama; Michitaka Kameyama (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions. - Martin Lukac; Marek A. Perkowski; Michitaka Kameyama (IEEE Congress on Evolutionary Computation, 2010)

An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. - Masanori Hariyama; Ryoto Tsuchiya; Shota Ishihara; Michitaka Kameyama (ERSA, 2010)

Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (ERSA, 2010)

Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. - Hasitha Muthumala Waidyasooriya; Daisuke Okumura; Masanori Hariyama; Michitaka Kameyama (ERSA, 2010)

Adaptive Selection of Intelligent Processing Modules and its Applications. - Martin Lukac; Michitaka Kameyama; Marek A. Perkowski (IC-AI, 2010)

Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals. - Akitaka Ishikawa; Nobuaki Okada; Michitaka Kameyama (ISMVL, 2010)

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. - Shota Ishihara; Noriaki Idobata; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2010)

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. - Shota Ishihara; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2010)

Foreword. - Michitaka Kameyama (IEICE Trans. Inf. Syst., 2010)

Group Testing Based Detection of Web Service DDoS Attackers. - Dalia Nashat; Xiaohong Jiang 001; Michitaka Kameyama (IEICE Trans. Commun., 2010)

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits. - Nobuaki Okada; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2010)

Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. - Hasitha Muthumala Waidyasooriya; Daisuke Okumura; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. - Yoshiya Komatsu; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (ASP-DAC, 2011)

High Performance Tag Singulation for Memory-Less RFID Systems. - Keyvan Kashkouli Nejad; Xiaohong Jiang 001; Michitaka Kameyama (ICC, 2011)

Non-blocking tag scanning for passive RFID localization. - Keyvan Kashkouli Nejad; Xiaohong Jiang 001; Michitaka Kameyama (ISDA, 2011)

Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation. - Martin Lukac; Ben Shuai; Michitaka Kameyama; D. Michael Miller (ISMVL, 2011)

Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics - Maarti nLukac; Marek A. Perkowski; Michitaka Kameyama (CoRR, 2011)

Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. - Shota Ishihara; Ryoto Tsuchiya; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2011)

Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing. - Kan Watanabe; Masaru Fukushi; Michitaka Kameyama (J. Inf. Process., 2011)

Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. - Hasitha Muthumala Waidyasooriya; Yosuke Ohbayashi; Masanori Hariyama; Michitaka Kameyama (IEEE Trans. Circuits Syst. Video Technol., 2011)

A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. - Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (IEEE Trans. Very Large Scale Integr. Syst., 2011)

FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. - Hasitha Muthumala Waidyasooriya; Yasuhiro Takei; Masanori Hariyama; Michitaka Kameyama (ISCAS, 2012)

Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. - Zhengfan Xia; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (ISCAS, 2012)

Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture. - Xu Bai; Michitaka Kameyama (ISMVL, 2012)

Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits. - Shogo Kisara; Michitaka Kameyama (ISMVL, 2012)

Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme. - Yoshichika Fujioka; Michitaka Kameyama (ISOCC, 2012)

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. - Yoshitaka Hiramatsu; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Tohru Nojiri; Kunio Uchiyama; Michitaka Kameyama (IEICE Trans. Electron., 2012)

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. - Hasitha Muthumala Waidyasooriya; Yosuke Ohbayashi; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2012)

Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. - Zhengfan Xia; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2012)

Driver's Intention Estimation Based on Bayesian Networks for a Highly-Safe Intelligent Vehicle. - Bo Sun; Michitaka Kameyama (J. Robotics Mechatronics, 2012)

A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme. - Xu Bai; Nobuaki Okada; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2012)

High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation? - Martin Lukac; Michitaka Kameyama; D. Michael Miller; Marek A. Perkowski (J. Multiple Valued Log. Soft Comput., 2012)

Natural image understanding using algorithm selection and high-level feedback. - Martin Lukac; Michitaka Kameyama; Kosuke Hiura (Intelligent Robots and Computer Vision: Algorithms and Techniques, 2013)

Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (EMBC, 2013)

Bayesian Network for algorithm selection: Real-world hierarchy for nodes reduction. - Martin Lukac; Michitaka Kameyama (iCAST/UMEDIA, 2013)

Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI. - Xu Bai; Michitaka Kameyama (ISMVL, 2013)

An Area-Efficient Multiple-Valued Reconfigurable VLSI Architecture Using an X-Net. - Xu Bai; Michitaka Kameyama (ISMVL, 2013)

Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format. - Maher Hawash; Martin Lukac; Michitaka Kameyama; Marek A. Perkowski (ISMVL, 2013)

Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences. - Martin Lukac; Michitaka Kameyama; Marek A. Perkowski; Pawel Kerntopf (ISMVL, 2013)

RFID-based localization with Non-Blocking tag scanning. - Keyvan Kashkouli Nejad; Xiaohong Jiang 001; Michitaka Kameyama (Ad Hoc Networks, 2013)

A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme. - Xu Bai; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2013)

A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits. - Xu Bai; Michitaka Kameyama (IEICE Trans. Electron., 2013)

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design. - Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2013)

Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators. - Yasuhiro Takei; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Quantum Finite State Machines - a Circuit Based Approach. - Martin Lukac; Michitaka Kameyama; Marek A. Perkowski (Int. J. Unconv. Comput., 2013)

Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures. - Shota Ishihara; Noriaki Idobata; Masanori Hariyama; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2013)

Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing. - Hasitha Muthumala Waidyasooriya; Daisuke Ono; Masanori Hariyama; Michitaka Kameyama (APCCAS, 2014)

Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits Patterns. - Martin Lukac; Maher Hawash; Michitaka Kameyama; Marek A. Perkowski; Pawel Kerntopf (DSD, 2014)

Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. - Shintaro Harada; Xu Bai; Michitaka Kameyama; Yoshichika Fujioka (ISMVL, 2014)

Analysis of Faults in Reversible Computing. - Martin Lukac; Michitaka Kameyama; Marek A. Perkowski; Pawel Kerntopf; Claudio Moraga (ISMVL, 2014)

Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network. - Xu Bai; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2014)

Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI. - Xu Bai; Michitaka Kameyama (IEICE Trans. Electron., 2014)

Synthesis of Quantum Arrays from Kronecker Functional Lattice Diagrams. - Martin Lukac; Dipal Shah; Marek A. Perkowski; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2014)

FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Yasuhiro Takei; Michitaka Kameyama (J. Comput. Eng., 2014)

Reversible, Information-Preserving Logic and Its Application. - Martin Lukac; Ben Shuai; Michitaka Kameyama; D. Michael Miller (J. Multiple Valued Log. Soft Comput., 2014)

Novel VLSI Architectures for Real-World Intelligent Systems. - Michitaka Kameyama (ISMVL, 2015)

Symbolic Segmentation Using Algorithm Selection. - Martin Lukac; Kamila Abdiyeva; Michitaka Kameyama (CoRR, 2015)

Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators. - Yasuhiro Takei; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

An algorithm selection based platform for image understanding using high-level symbolic feedback and machine learning. - Martin Lukac; Michitaka Kameyama (Int. J. Mach. Learn. Cybern., 2015)

Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. - Zhengfan Xia; Masanori Hariyama; Michitaka Kameyama (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Reasoning and Algorithm Selection Augmented Symbolic Segmentation. - Martin Lukac; Kamila Abdiyeva; Michitaka Kameyama (CoRR, 2016)

On Minimal Accuracy Algorithm Selection in Computer Vision and Intelligent Systems. - Martin Lukac; Kamila Abdiyeva; Michitaka Kameyama (CoRR, 2016)

Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic. - Katsuhiko Shimabukuro; Michitaka Kameyama (ISMVL, 2017)

Live-feeling communication: Multi-algorithm approach to the estimation of human intentions. - Martin Lukac; Michitaka Kameyama; Yevgeniya Migranova (SMC, 2017)

Building a Completely Reversible Computer. - Martin Lukac; Gerhard W. Dueck; Michitaka Kameyama; Anirban Pathak (CoRR, 2017)

Context Based Visual Content Verification. - Martin Lukac; Aigerim Bazarbayeva; Michitaka Kameyama (CoRR, 2017)

CNOT-Measure Quantum Neural Networks. - Martin Lukac; Kamila Abdiyeva; Michitaka Kameyama (ISMVL, 2018)

High-Accuracy Scene Recognition and Its Application to Highly-Safe Intelligent Systems. - Kenichi Takada; Michitaka Kameyama (SMC, 2018)

Selecting Algorithms Without Meta-features. - Martin Lukac; Ayazkhan Bayanov; Albina Li; Kamila Abdiyeva; Nadira Izbassarova; Magzhan Gabidolla; Michitaka Kameyama (ICPR Workshops (4), 2020)

Optimization of LNN Reversible Circuits Using an Analytic Sifting Method. - Martin Lukac; Pawel Kerntopf; Michitaka Kameyama (J. Circuits Syst. Comput., 2021)

Approximate Function Classification. - Martin Lukac; Krzysztof Podlaski; Michitaka Kameyama (ICCS (1), 2022)

Verification Based Algorithm Selection. - Martin Lukac; Michitaka Kameyama (IDT, 2023)

Ternary Function Classification Using Machine Learning. - Martin Lukac; Krzysztof Podlaski; Shinobu Nagayama; Michitaka Kameyama (ISMVL, 2024)

Geometric Refactoring of Quantum and Reversible Circuits Using Graph Algorithms. - Martin Lukac; Saadat Nursultan; Georgiy Krylov; Oliver Keszöcze; Abilmansur Rakhmettulayev; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2024)