Board Test DFT Model for Computer Products. - Mick Tegethoff; T. E. Figal; S. W. Hird (ITC, 1992)

IEEE 1149.1: How to Justify Implementation. - Mick Tegethoff (ITC, 1993)

Defects, Fault Coverage, Yield and Cost in Board Manufacturing. - Mick Tegethoff; Tom Chen 001 (ITC, 1994)

Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. - Mick Tegethoff; Tom Chen 001 (ITC, 1994)

IEEE Std 1149.1: Where Are We? Where From Here? - Mick Tegethoff; Kenneth P. Parker (IEEE Des. Test Comput., 1995)

Issues in Optimizing the Test Process - A Telecom Case Study. - Felix Frayman; Mick Tegethoff; Brenton White (ITC, 1996)

ASIC Yield Estimation at Early Design Cycle. - Von-Kyoung Kim; Mick Tegethoff; Tom Chen 001 (ITC, 1996)

Opens Board Test Coverage: When is 99% Really 40%? - Mick Tegethoff; Kenneth P. Parker; Ken Lee (ITC, 1996)

Sensitivity Analysis of Critical Parameters in Board Test. - Mick Tegethoff; Tom Chen 001 (IEEE Des. Test Comput., 1996)

ASIC Manufacturing Test Cost Prediction at Early Design Stage. - Von-Kyoung Kim; Tom Chen 001; Mick Tegethoff (ITC, 1997)

Simulation Techniques for the Manufacturing Test of MCMs. - Mick Tegethoff; Tom Chen 001 (J. Electron. Test., 1997)

Fault Coverage Estimation for Early Stage of VLSI Design. - Von-Kyoung Kim; Tom Chen 001; Mick Tegethoff (Great Lakes Symposium on VLSI, 1999)

A new methodology for improved tester utilization. - Ajay Khoche; Rohit Kapur; David Armstrong; Thomas W. Williams; Mick Tegethoff; Jochen Rivoir (ITC, 2001)

An Economic Analysis and ROI Model for Nanometer Test. - Brion L. Keller; Mick Tegethoff; Thomas Bartenstein; Vivek Chickermane (ITC, 2004)

Not all Delay Tests Are the Same - SDQL Model Shows True-Time. - Anis Uzzaman; Mick Tegethoff; Bibo Li; Kevin McCauley; Shuji Hamada; Yasuo Sato (ATS, 2006)

OCI: Open Compression Interface. - Bruce Cory; Rohit Kapur; Mick Tegethoff; Mark Kassab; Brion L. Keller; Kee Sup Kim; Dwayne Burek; Steven F. Oakland; Benoit Nadeau-Dostie (ITC, 2006)