Miguel Areias

Orcid: 0000-0003-1589-3174

Affiliations:
  • University of Porto, Portugal


According to our database1, Miguel Areias authored at least 25 papers between 2009 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2022
On the correctness of a lock-free compression-based elastic mechanism for a hash trie design.
Computing, 2022

2021
On the implementation of memory reclamation methods in a lock-free hash trie design.
J. Parallel Distributed Comput., 2021

On the correctness and efficiency of a novel lock-free hash trie map design.
J. Parallel Distributed Comput., 2021

Towards an Elastic Lock-Free Hash Trie Design.
Proceedings of the 20th International Symposium on Parallel and Distributed Computing, 2021

2020
A Compression-Based Design for Higher Throughput in a Lock-Free Hash Map.
Proceedings of the Euro-Par 2020: Parallel Processing, 2020

2019
Multi-dimensional lock-free arrays for multithreaded mode-directed tabling in Prolog.
Concurr. Comput. Pract. Exp., 2019

Memory Reclamation Methods for Lock-Free Hash Tries.
Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019

2018
Table space designs for implicit and explicit concurrent tabled evaluation.
Theory Pract. Log. Program., 2018

On Extending a Fixed Size, Persistent and Lock-Free Hash Map Design to Store Sorted Keys.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

2017
On scaling dynamic programming problems with a multithreaded tabling Prolog system.
J. Syst. Softw., 2017

On the Implementation of a Cloud-Based Computing Test Bench Environment for Prolog Systems.
Inf., 2017

Towards an Automated Test Bench Environment for Prolog Systems.
Proceedings of the 6th Symposium on Languages, Applications and Technologies, 2017

Towards a Lock-Free, Fixed Size and Persistent Hash Map Design.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

2016
A Lock-Free Hash Trie Design for Concurrent Tabled Logic Programs.
Int. J. Parallel Program., 2016

2015
Multithreaded Tabling for Logic Programming
PhD thesis, 2015

Batched Evaluation of Full-Sharing Multithreaded Tabling.
Proceedings of the Languages, Applications and Technologies - 4th International Symposium, 2015

2014
A Simple and Efficient Lock-Free Hash Trie Design for Concurrent Tabling.
CoRR, 2014

On the Correctness and Efficiency of Lock-Free Expandable Tries for Tabled Logic Programs.
Proceedings of the Practical Aspects of Declarative Languages, 2014

2013
Batched evaluation of linear tabled logic programs.
Comput. Sci. Inf. Syst., 2013

2012
Towards multi-threaded local tabling using a common table space.
Theory Pract. Log. Program., 2012

On Extending a Linear Tabling Framework to Support Batched Scheduling.
Proceedings of the 1st Symposium on Languages, Applications and Technologies, 2012

An Efficient and Scalable Memory Allocator for Multithreaded Tabled Evaluation of Logic Programs.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

2011
On combining linear-based strategies for tabled evaluation of logic programs.
Theory Pract. Log. Program., 2011

2010
An Efficient Implementation of Linear Tabling Based on Dynamic Reordering of Alternatives.
Proceedings of the Practical Aspects of Declarative Languages, 2010

2009
On Improving the Efficiency of Deterministic Calls and Answers in Tabled Logic Programs.
Proceedings of the Progress in Artificial Intelligence, 2009


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