A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration. - Miguel Gandara; Paridhi Gulati; Nan Sun 001 (A-SSCC, 2017)

A pipelined SAR ADC reusing the comparator as residue amplifier. - Miguel Gandara; Wenjuan Guo; Xiyuan Tang; Long Chen 004; Yeonam Yoon; Nan Sun 001 (CICC, 2017)

A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure. - Shaolan Li; Bo Qiao 005; Miguel Gandara; Nan Sun 001 (ISSCC, 2018)

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. - Shaolan Li; Bo Qiao 005; Miguel Gandara; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2018)

6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology. - Tamer A. Ali 001; Ehung Chen; Henry Park; Ramy Yousry; Yu-Ming Ying; Mohammed Abdullatif; Miguel Gandara; Chun-Cheng Liu; Po-Shuan Weng; Huan-Sheng Chen; Mohammad Elbadry; Qaiser Nehal; et al. (ISSCC, 2020)

56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology. - Tamer A. Ali 001; Mohammed Abdullatif; Henry Park; Ehung Chen; Ramy Awad; Miguel Gandara (CICC, 2021)

A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. - Abhishek Mukherjee; Miguel Gandara; Xiangxing Yang; Linxiao Shen; Xiyuan Tang; Chen-Kai Hsu; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. - Ahmet Faruk Budak; Miguel Gandara; Wei Shi 011; David Z. Pan; Nan Sun 001; Bo Liu 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET. - Henry Park; Mohammed Abdullatif; Ehung Chen; Ahmed Elmallah; Qaiser Nehal; Miguel Gandara; Tsz-Bin Liu; Amr Khashaba; Joonyeong Lee; Chih-Yi Kuan; Dhinessh Ramachandran; Ruey-Bo Sun; et al. (ISSCC, 2023)

Design of a Two-Stage Miller-Compensated Operational Amplifier Using an EDA Tool-Centered Approach. - Yijia Hao; Miguel Gandara; Srinjoy Mitra; Sandy Cochran; Bo Liu 003 (SMACD, 2024)

7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET. - Ehung Chen; Henry Park; Mohammed Abdullatif; Miguel Gandara; Ahmed ElShater; Amr Khashaba; Shih-Hao Huang; Tsz-Bin Liu; Atharav Atharav; Joonyeong Lee; Qaiser Nehal; Mohamed Megahed; et al. (ISSCC, 2025)

7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET. - Henry Park; Qaiser Nehal; Miguel Gandara; Atharav Atharav; Joonyeong Lee; Jengfeng Li; Tamer Ali (ISSCC, 2025)

An AI-driven EDA Algorithm-Empowered VCO and LDO Co-Design Method. - Yijia Hao; Maarten Strackx; Miguel Gandara; Sandy Cochran; Bo Liu 003 (SMACD, 2025)