A Focal Plane Architecture for Motion Computation. - Miguel O. Arias-Estrada; Marc Tremblay; Denis Poussart (Real Time Imaging, 1996)

FPGA Based Computer Vision Camera. - A. Lecerf; François Vachon; D. Ouellet; Miguel O. Arias-Estrada (FPGA, 1999)

An FPGA Architecture for High Speed Edge and Corner Detection. - César Torres-Huitzil; Miguel O. Arias-Estrada (CAMP, 2000)

Compact Spiking Neural Network Implementation in FPGA. - Selene Maya; M. Rocio Reynoso; César Torres-Huitzil; Miguel O. Arias-Estrada (FPL, 2000)

Bragg Curve Identification Using a Neural Network. - Juan Jaime Vega; M. Rocio Reynoso; Miguel Arias-Estrada; Leopoldo Altamirano Robles (IJCNN (4), 2000)

Multiple Stereo Matching Using an Extended Architecture. - Miguel Arias-Estrada; Juan M. Xicoténcatl Pérez (FPL, 2001)

Real-time field programmable gate array architecture for computer vision. - Miguel O. Arias-Estrada; César Torres-Huitzil (J. Electronic Imaging, 2001)

An FPGA Co-processor for Real-Time Visual Tracking. - Miguel Arias-Estrada; Eduardo Rodríguez-Palacios (FPL, 2002)

A reconfigurable vision system for real-time applications. - César Torres-Huitzil; Selene Maya-Rueda; Miguel O. Arias-Estrada (FPT, 2002)

FPGA Processor for Real-Time Optical Flow Computation. - Selene Maya-Rueda; Miguel O. Arias-Estrada (FPL, 2003)

Configurable Hardware Architecture for Real-Time Window-Based Image Processing. - César Torres-Huitzil; Miguel O. Arias-Estrada (FPL, 2003)

FPGA Based High Density Spiking Neural Network Array. - Juan M. Xicoténcatl Pérez; Miguel Arias-Estrada (FPL, 2003)

Three video applications using an FPGA based pyramid implementation: Tracking, Mosaics and Stabilization. - Marco Aurelio Nuño-Maganda; Miguel O. Arias-Estrada; Claudia Feregrino Uribe (FPT, 2003)

Real-time image processing with a compact FPGA-based systolic architecture. - César Torres-Huitzil; Miguel O. Arias-Estrada (Real Time Imaging, 2004)

Super-resolution with integrated radial distortion correction. - Liz Castillo-Jimenez; Miguel Arias-Estrada (ENC, 2005)

3D Recovery with Free Hand Camera Motion. - Gerardo Sosa-Ramirez; Miguel Arias-Estrada (ENC, 2005)

Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling. - Marco Aurelio Nuño-Maganda; Miguel O. Arias-Estrada (ReConFig, 2005)

FPGA-based customizable systolic architecture for image processing applications. - Griselda Saldaña; Miguel Arias-Estrada (ReConFig, 2005)

FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing. - César Torres-Huitzil; Miguel O. Arias-Estrada (EURASIP J. Adv. Signal Process., 2005)

Stereo Analysis Extension Based on BRDF Reciprocity. - Alicia Morales-Reyes; Miguel O. Arias-Estrada (CONIELECOMP, 2006)

Customizable FPGA-based architecture for video applications in real time. - Griselda Saldaña; Miguel Arias-Estrada (FPT, 2006)

Iterative Closest SIFT Formulation for Robust Feature Matching. - Rafael Lemuz-López; Miguel Arias-Estrada (ISVC (2), 2006)

A Domain Reduction Algorithm for Incremental Projective Reconstruction. - Rafael Lemuz-López; Miguel Arias-Estrada (ISVC (2), 2006)

Real Time FPGA-based Architecture for Video Applications. - Griselda Saldaña; Miguel Arias-Estrada (ReConFig, 2006)

High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs. - Marco Aurelio Nuño-Maganda; Miguel O. Arias-Estrada; César Torres-Huitzil (FPT, 2007)

Compact FPGA-based systolic array architecture suitable for vision systems. - Griselda Saldaña; Miguel Arias-Estrada (Int. J. High Perform. Syst. Archit., 2007)

Creation of a 3D Robot Model and its Integration to a Microsoft Robotics Studio Simulation. - M. Alejandra Menéndez O.; D. Sosa G.; Miguel O. Arias-Estrada; A. Espinosa M.; J. E. Lara R. (SCSS (2), 2008)

A Low-Level Image Processing Algorithms Accelerator Platform. - Griselda Saldaña; Miguel Arias-Estrada (CONIELECOMP, 2008)

Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity. - César Torres-Huitzil; Bernard Girau; Miguel O. Arias-Estrada (ICANN (2), 2008)

Ranking Corner Points by the Angular Difference between Dominant Edges. - Rafael Lemuz-López; Miguel Arias-Estrada (ICVS, 2008)

Hardware/Software FPGA Architecture for Robotics Applications. - Juan Carlos Moctezuma Eugenio; Miguel Arias-Estrada (ARC, 2009)

Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms. - Marco Aurelio Nuño-Maganda; Miguel O. Arias-Estrada; César Torres-Huitzil; Bernard Girau (IJCNN, 2009)

Parallel Processor for 3D Recovery from Optical Flow. - Jose Hugo Barron-Zambrano; Fernando Martin del Campo-Ramirez; Miguel O. Arias-Estrada (Int. J. Reconfigurable Comput., 2009)

Input and/or output pruning of composite length FFTs using a DIF-DIT transform decomposition. - Modesto G. Medina-Meléndrez; Miguel O. Arias-Estrada; Albertina Castro (IEEE Trans. Signal Process., 2009)

Embedded attitude control system for the educative satellite SATEDU. - Mario Alberto Mendoza-Barcenas; Eduardo Vizcaino Torres; Esaú Vicente Vivas; Miguel Arias-Estrada; Ignacio Mendoza Nucamendi; Jose Angel Colin Robles (CONIELECOMP, 2012)

Acceleration of the reflectance field acquisition using independent component analysis. - Maria Luisa Rosas-Cholula; Miguel O. Arias-Estrada (CONIELECOMP, 2012)

Using a Scaling Factor in O(1/N) for the fixed-point implementation of the second-order goertzel filter. - Modesto G. Medina-Meléndrez; Miguel O. Arias-Estrada; Albertina Castro (ISCAS, 2012)

A Hardware Architecture for Image Clustering Using Spiking Neural Networks. - Marco Aurelio Nuño-Maganda; Miguel O. Arias-Estrada; César Torres-Huitzil; Héctor Hugo Avilés-Arriaga; Yahir Hernández-Mier; Miguel Morales-Sandoval (ISVLSI, 2012)

Integrated three-dimensional reconstruction using reflectance fields - Maria-Luisa Sosas; Miguel-Octavio Arias (CoRR, 2012)

FPGA-based detection of SIFT interest keypoints. - Leonardo Chang 001; José Hernández Palancar; Luis Enrique Sucar; Miguel O. Arias-Estrada (Mach. Vis. Appl., 2013)

Partial Shape Matching and Retrieval under Occlusion and Noise. - Leonardo Chang 001; Miguel O. Arias-Estrada; José Hernández Palancar; Luis Enrique Sucar (CIARP, 2014)

An Efficient Shape Feature Extraction, Description and Matching Method Using GPU. - Leonardo Chang 001; Miguel O. Arias-Estrada; José Hernández Palancar; Luis Enrique Sucar (ICPRAM (Selected Papers), 2014)

LISF: An Invariant Local Shape Features Descriptor Robust to Occlusion. - Leonardo Chang 001; Miguel O. Arias-Estrada; Luis Enrique Sucar; José Hernández Palancar (ICPRAM, 2014)

Sequential application of viscous opening and lower leveling for three-dimensional brain extraction on magnetic resonance imaging T1. - Jorge Domingo Mendiola-Santibañez; Martín Gallegos-Duarte; Miguel Octavio Arias-Estrada; Israel Marcos Santillán-Méndez; Juvenal Rodríguez-Reséndiz; Iván Ramón Terol-Villalobos (J. Electronic Imaging, 2014)

Assessing the Distinctiveness and Representativeness of Visual Vocabularies. - Leonardo Chang 001; Airel Pérez Suárez; Máximo Rodríguez-Collada; José Hernández Palancar; Miguel O. Arias-Estrada; Luis Enrique Sucar (CIARP, 2015)

An FPGA Correlation-Edge Distance approach for disparity map. - Abiel Aguilar-González; Madaín Pérez Patricio; Miguel O. Arias-Estrada; Jorge-Luis Camas-Anzueto; Héctor-Ricardo Hernandez-de Leon; Avisai Sanchez-Alegria (CONIELECOMP, 2015)

Morphological Filtering Algorithm for Restoring Images Contaminated by Impulse Noise. - Jorge D. Mendiola-Santibañez; Miguel O. Arias-Estrada; Israel Marcos Santillán-Méndez; Juvenal Rodríguez-Reséndiz; Martín Gallegos-Duarte; Domingo José Gomez-Melendez; Iván R. Terol-Villalobos (Computación y Sistemas, 2015)

Algoritmo evolutivo paralelo para aplicaciones en tomografía sísmica. - Eustolia Carreón; José Federico Ramírez-Cruz; Miguel O. Arias-Estrada; Edmundo Bonilla Huerta; Roberto Morales-Caporal (Res. Comput. Sci., 2015)

An FPGA Stereo Matching Processor Based on the Sum of Hamming Distances. - Abiel Aguilar-González; Miguel O. Arias-Estrada (ARC, 2016)

Towards a smart camera for monocular SLAM. - Abiel Aguilar-González; Miguel O. Arias-Estrada (ICDSC, 2016)

Dominant plane recognition in interior scenes from a single image. - J. A. de Jesús Osuna-Coutiño; José Martínez-Carranza; Miguel O. Arias-Estrada; Walterio W. Mayol-Cuevas (ICPR, 2016)

Dense mapping for monocular-SLAM. - Abiel Aguilar-González; Miguel O. Arias-Estrada (IPIN, 2016)

Enhancing 3D Mapping via Real-Time Superpixel-based Segmentation. - Claudia Cruz Martinez; José Martínez-Carranza; Walterio W. Mayol-Cuevas; Miguel O. Arias-Estrada (ISMAR Adjunct, 2016)

I Want to Change My Floor: Dominant Plane Recognition from a Single Image to Augment the Scene. - J. A. de Jesús Osuna-Coutiño; Claudia Cruz Martinez; José Martínez-Carranza; Miguel O. Arias-Estrada; Walterio W. Mayol-Cuevas (ISMAR Adjunct, 2016)

An FPGA stereo matching unit based on fuzzy logic. - Madaín Pérez Patricio; Abiel Aguilar-González; Miguel O. Arias-Estrada; Héctor-Ricardo Hernandez-de Leon; Jorge-Luis Camas-Anzueto; J. A. de Jesús Osuna-Coutiño (Microprocess. Microsystems, 2016)

Dense Feature Matching Core for FPGA-based Smart Cameras. - Abiel Aguilar-González; Miguel Arias-Estrada; François Berry (ICDSC, 2017)

Camera Pose Estimation Suitable for Smart Cameras. - Abiel Aguilar-González; Miguel Arias-Estrada; François Berry (ICDSC, 2017)

Deep Learning Pulsed-based Convolutional Neuroprocessor Architecture on FPGAs. - Walther Carballo-Hernández; Miguel Arias-Estrada (ICDSC, 2017)

GPU-based Visual Odometry for Autonomous Vehicle Applications. - J. A. de Jesús Osuna-Coutiño; Abiel Aguilar-González; Miguel Arias-Estrada (ICDSC, 2017)

Improving visual vocabularies: a more discriminative, representative and compact bag of visual words. - Leonardo Chang 001; Airel Pérez Suárez; José Hernández Palancar; Miguel Arias-Estrada; Luis Enrique Sucar (Informatica (Slovenia), 2017)

Robust feature extraction algorithm suitable for real-time embedded applications. - Abiel Aguilar-González; Miguel Arias-Estrada; François Berry (J. Real Time Image Process., 2018)

Towards Embedded Heterogeneous FPGA-GPU Smart Camera Architectures for CNN Inference. - Walther Carballo-Hernández; François Berry; Maxime Pelcat; Miguel Arias-Estrada (ICDSC, 2019)

An FPGA 2D-convolution unit based on the CAPH language. - Abiel Aguilar-González; Miguel Arias-Estrada; Madaín Pérez Patricio; Jorge-Luis Camas-Anzueto (J. Real Time Image Process., 2019)

The fastest visual ego-motion algorithm in the west. - Abiel Aguilar-González; Miguel Arias-Estrada; François Berry; J. A. de Jesús Osuna-Coutiño (Microprocess. Microsystems, 2019)

Depth from a Motion Algorithm and a Hardware Architecture for Smart Cameras. - Abiel Aguilar-González; Miguel Arias-Estrada; François Berry (Sensors, 2019)

A Variable Sampling-Time Method for Elliptical Orbit Motion Prediction in Nanosatellites. - Berenice Rodríguez-Pedroza; Miguel O. Arias-Estrada; José E. Mendoza-Torres (IEEE Access, 2021)

Real-time multi-window stereo matching algorithm with fuzzy logic. - Héctor-Daniel Vázquez-Delgado; Madaín Pérez Patricio; Abiel Aguilar-González; Miguel Octavio Arias-Estrada; Marco-Antonio Palacios-Ramos; Jorge-Luis Camas-Anzueto; Antonio Pérez Cruz; Sabino Velázquez-Trujillo (IET Comput. Vis., 2021)