A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array. - Jung-Sik Kim; Kyung-Woo Nam; Chi Sung Oh; Han Gu Sohn; Donghyuk Lee; Sooyoung Kim; Jong-Wook Park; Yongjun Kim; Mi-Jo Kim; Jin-Guk Kim; Hocheol Lee; Jinhyoung Kwon; et al. (IEEE J. Solid State Circuits, 2008)

100MHz-to-1GHz open-loop ADDLL with fast lock-time for mobile applications. - Mi-Jo Kim; Lee-Sup Kim (CICC, 2010)

A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications. - Mi-Jo Kim; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. - Yong-Cheol Bae; Joon-Young Park; Sang Jae Rhee; Seung-Bum Ko; Yonggwon Jeong; Kwang-Sook Noh; Young Hoon Son; Jaeyoun Youn; Yonggyu Chu; Hyunyoon Cho; Mijo Kim; Daesik Yim; et al. (ISSCC, 2012)

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (ISSCC, 2018)