Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification. - Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Yvon Trinquet (ETFA, 2006)

Simulator generation using an automaton based pipeline model for timing analysis. - Rola Kassem; Mikaël Briday; Jean-Luc Béchennec; Yvon Trinquet; Guillaume Savaton (IMCSIT, 2008)

Instruction set simulator generation using HARMLESS, a new hardware architecture description language. - Rola Kassem; Mikaël Briday; Jean-Luc Béchennec; Yvon Trinquet; Guillaume Savaton (SimuTools, 2009)

ViPER: a lightweight approach to the simulation of distributed and embedded software. - Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Florent Pavin; Fabien Juif (SimuTools, 2010)

Extending Harmless architecture description language for embedded real-time systems validation. - Jean-Luc Béchennec; Mikaël Briday; Valere Alibert (SIES, 2011)

An Architecture Description Language for Embedded Hardware Platforms. - Guillaume Savaton; Jean-Luc Béchennec; Mikaël Briday; Rola Kassem (Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2011)

Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. - Rola Kassem; Mikaël Briday; Jean-Luc Béchennec; Guillaume Savaton; Yvon Trinquet (J. Syst. Archit., 2012)

Device driver synthesis for embedded systems. - Julien Tanguy; Jean-Luc Béchennec; Mikaël Briday; Sebastien Dube; Olivier H. Roux (ETFA, 2013)

Reactive embedded device driver synthesis using logical timed models. - Julien Tanguy; Jean-Luc Béchennec; Mikaël Briday; Olivier H. Roux (SIMULTECH, 2014)

Improving processor hardware compiled cycle accurate simulation using program abstraction. - Adrien Bullich; Mikaël Briday; Jean-Luc Béchennec; Yvon Trinquet (SimuTools, 2014)

Hardware runtime verification of embedded software in SoPC. - Dimitry Solet; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Sébastien Pillement (SIES, 2016)

BEST: a Binary Executable Slicing Tool. - Armel Mangean; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou (WCET, 2016)

WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. - Armel Mangean; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou (VECoS, 2017)

HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems. - Dimitry Solet; Jean-Luc Béchennec; Mikaël Briday (AHS, 2018)

Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. - Dimitry Solet; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Sébastien Pillement (EDCC, 2018)

Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design. - Rémi Parrot; Mikaël Briday; Olivier H. Roux (Petri Nets, 2021)

Pipeline Optimization using a Cost Extension of Timed Petri Nets. - Rémi Parrot; Mikaël Briday; Olivier H. Roux (ARITH, 2021)

Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds. - Vincent Lostanlen; Antoine Bernabeu; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Mathieu Lagrange (Audio Mostly Conference, 2021)

Securing a RISC-V architecture: A dynamic approach. - Sébastien Pillement; Maria Mendez Real; J. Pottier; T. Nieddu; Bertrand Le Gal; Sébastien Faucou; Jean-Luc Béchennec; Mikaël Briday; Sylvain Girbal; Jimmy Le Rhun; Olivier Gilles; Daniel Gracia Pérez; et al. (DATE, 2023)

Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems. - Antoine Bernabeu; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Olivier H. Roux (Discret. Event Dyn. Syst., 2023)

Design and verification of pipelined circuits with Timed Petri Nets. - Rémi Parrot; Mikaël Briday; Olivier H. Roux (Discret. Event Dyn. Syst., 2023)

SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems. - Hugo Reymond; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Isabelle Puaut; Erven Rohou (CGO, 2024)

EarlyBird: Energy belongs to those who wake up early. - Hugo Reymond; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Isabelle Puaut; Erven Rohou (RTCSA, 2024)

A Study in Specification and Hardware Runtime Verification of Critical Embedded Software. - Dimitry Solet; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Sébastien Pillement (IEEE Trans. Dependable Secur. Comput., 2025)