Process dependence of BTI reliability in advanced HK MG stacks. - Xavier Garros; Mikaël Cassé; M. Rafik; Claire Fenouillet-Béranger; Gilles Reimbold; François Martin; Claudia Wiemer; F. Boulanger (Microelectron. Reliab., 2009)

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs. - Masahiro Koyama; Mikaël Cassé; Remi Coquand; Sylvain Barraud; Hiroshi Iwai; Gérard Ghibaudo; Gilles Reimbold (ESSDERC, 2012)

Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations. - Remi Coquand; Sylvain Barraud; Mikaël Cassé; Masahiro Koyama; Virginie Maffini-Alvaro; Marie-Pierre Samson; Lucie Tosti; Xavier Mescot; Gérard Ghibaudo; Stéphane Monfray; Frédéric Boeuf; Olivier Faynot; et al. (ESSDERC, 2013)

Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs. - Masahiro Koyama; Mikaël Cassé; Remi Coquand; Sylvain Barraud; Gérard Ghibaudo; Hiroshi Iwai; Gilles Reimbold (ESSDERC, 2013)

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. - François Andrieu; Mikaël Cassé; E. Baylac; P. Perreau; O. Nier; Denis Rideau; R. Berthelon; Franck Pourchon; A. Pofelski; Barbara De Salvo; C. Gallon; Vincent Mazzocchi; et al. (ESSDERC, 2014)

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration. - Claire Fenouillet-Béranger; Bernard Previtali; Perrine Batude; Fabrice Nemouchi; Mikaël Cassé; Xavier Garros; Lucie Tosti; Nils Rambal; Dominique Lafond; Hugo Dansas; Luca Pasini; Laurent Brunet; et al. (ESSDERC, 2014)

Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model. - J. Pelloux-Prayer; Mikaël Cassé; François Triozon; Sylvain Barraud; Yann-Michel Niquet; J.-L. Rouviere; Olivier Faynot; Gilles Reimbold (ESSDERC, 2015)

Analog performance of strained SOI nanowires down to 10K. - Bruna Cardoso Paz; Marcelo Antonio Pavanello; Mikaël Cassé; Sylvain Barraud; Gilles Reimbold; Maud Vinet; Olivier Faynot (ESSDERC, 2016)

Drain current model for short-channel triple gate junctionless nanowire transistors. - Bruna Cardoso Paz; Mikaël Cassé; Sylvain Barraud; Gilles Reimbold; Olivier Faynot; F. Avila-Herrera; Antonio Cerdeira; Marcelo Antonio Pavanello (Microelectron. Reliab., 2016)

Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices. - Jessy Micout; Quentin Rafhay; Xavier Garros; Mikaël Cassé; Jean Coignus; Luca Pasini; Cao-Minh Vincent Lu; Nils Rambal; Claire Fenouillet-Béranger; Laurent Brunet; G. Romano; R. Gassilloud; et al. (ESSDERC, 2017)

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K. - Bruna Cardoso Paz; Renan Trevisoli Doria; Mikaël Cassé; Sylvain Barraud; Gilles Reimbold; Maud Vinet; Olivier Faynot; Marcelo Antonio Pavanello (Microelectron. Reliab., 2017)

Performance & reliability of 3D architectures (πfet, Finfet, Ωfet). - Antoine Laurent; Xavier Garros; Sylvain Barraud; J. Pelloux-Prayer; Mikaël Cassé; Fred Gaillard; X. Federspiel; David Roy 001; E. Vincent; Gérard Ghibaudo (IRPS, 2018)

MOS technology for quantum computing: recent progress and perspectives for scaling up. - Louis Hutin; Benoit Bertrand; Heimanu Niebojewski; Pierre-André Mortemousque; Mikaël Cassé; Gérard Billiot; Xavier Jehl; Romain Maurand; Matias Urdampilleta; Yann-Michel Niquet; S. De Franceschi; Tristan Meunier; et al. (DRC, 2021)

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors. - Michelly de Souza; Sylvain Barraud; Mikaël Cassé; Maud Vinet; Olivier Faynot; Marcelo Antonio Pavanello (ESSDERC, 2021)

Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration. - Tadeu Mota Frutuoso; Jose Lugo-Alvarez; Xavier Garros; Laurent Brunet; Joris Lacord; Louis Gerrer; Mikaël Cassé; Edoardo Catapano; Claire Fenouillet-Béranger; François Andrieu; Fred Gaillard; Philippe Ferrari (IRPS, 2021)

Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K. - Lauriane Contamin; Mikaël Cassé; Xavier Garros; Fred Gaillard; Maud Vinet; Philippe Galy; André Juge; Emmanuel Vincent 004; Silvano De Franceschi; Tristan Meunier (IRPS, 2022)

Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration. - Tadeu Mota Frutuoso; Xavier Garros; Perrine Batude; Laurent Brunet; Joris Lacord; Benoit Sklénard; V. Lapras; Claire Fenouillet-Béranger; M. Ribotta; A. Magalhaes-Lucas; J. Kanyandekwe; R. Kies; et al. (VLSI Technology and Circuits, 2022)

Specificities of linear Si QD arrays integration and characterization. - Heimanu Niebojewski; Benoit Bertrand; Etienne Nowak; Thomas Bedecarrats; Bruna Cardoso Paz; Lauriane Contamin; Pierre-André Mortemousque; V. Labracherie; L. Brevard; H. Sahin; Jean Charbonnier; C. Thomas; et al. (VLSI Technology and Circuits, 2022)

RF performance of Standard, High-Resistivity and Trap-Rich Silicon substrates down to cryogenic temperature. - Quentin Berlingard; M. Moulin; Jean-Philippe Michel; T. Fache; Ismael Charlet; C. Plantier; Z. Chalupa; Jose Lugo-Alvarez; Jean-Pierre Raskin; Louis Hutin; Mikaël Cassé (ESSDERC, 2023)

Transport characterization of CMOS-based devices fabricated with isotopically-enriched 28Si for spin qubit applications. - G. Elbaz; Mikaël Cassé; V. Labracherie; G. Roussely; Benoit Bertrand; Heimanu Niebojewski; Maud Vinet; F. Balestro; Matias Urdampilleta; Tristan Meunier; Bruna Cardoso Paz (ESSDERC, 2023)

Noise modeling using look-up tables and DC measurements for cryogenic applications. - Giovani Britton; Salvador Mir; Estelle Lauga-Larroze; Benjamin Dormieu; Quentin Berlingard; Mikaël Cassé; Philippe Galy (VLSI-SoC, 2023)

Experimental Decomposition of the Carrier Mobility in the Conduction Planes of 2-Level Stacked Nanowires. - Giovanni Almeida Matos; Jaime CalÇade Rodrigues; Michelly de Souza; Mikaël Cassé; Sylvain Barraud; Olivier Faynot; Marcelo Antonio Pavanello (CCE, 2024)

LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching. - Giovani Britton; Salvador Mir; Estelle Lauga-Larroze; Benjamin Dormieu; Jose Lugo; Joao Azevedo; Sebastien Sadlo; Quentin Berlingard; Mikaël Cassé; Philippe Galy (NewCAS, 2024)

Self-Heating Effects in FDSOI Transistors at Cryogenic Temperature: A Spatial and Temporal Experimental Study (Invited). - Mikaël Cassé; Flávio Enrico Bergamaschi; Quentin Berlingard (IRPS, 2025)

Cryogenic Circuit Performance Prediction Using Design-Oriented Model (SEKV) On 22nm FDSOI. - Brian Martinez; Hung-Chi Han; Flávio Enrico Bergamaschi; Quentin Schmidt; Antoine Faurie; Edoardo Charbon; Yvain Thonnart; Baptiste Jadot; Xavier Jehl; Mikaël Cassé; Christian C. Enz; Franck Badets (ISCAS, 2025)