Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links. - Mike Bichan; Anthony Chan Carusone (ISCAS, 2007)

A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing. - Mike Bichan; Anthony Chan Carusone (CICC, 2008)

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC. - Mike Bichan; Dustin Dunwell; Qiwei Wang; Anthony Chan Carusone (ISCAS, 2014)

A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol. - Mike Bichan; Clifford Ting; Bahram Zand; Jing Wang; Ruslana Shulyzki; James Guthrie; Katya Tyshchenko; Junhong Zhao; Alireza Parsafar; Eric Liu; Aynaz Vatankhahghadim; Shaham Sharifian; et al. (CICC, 2020)

A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm. - Bahram Zand; Mike Bichan; Alireza Mahmoodi; Mansour Shashaani; Jing Wang; Ruslana Shulyzki; James Guthrie; Katya Tyshchenko; Junhong Zhao; Eric Liu; Nima Soltani; Al Freeman; et al. (ISSCC, 2022)

2.3 Granite Rapids-D: Intel Xeon 6 SoC for vRAN, Edge, Networking, and Storage. - Raj R. Varada; Rohini Krishnan; Ajith Subramonia; Rathish Chandran; Kalyana Chakravarthy; Uttpal D. Desai; Sumedha Limaye; Puneesh Puri; David R. Mulvihill; Mike Bichan; Martin Koolhaas; Vijayalakshmi Ramachandran; et al. (ISSCC, 2025)