A general model of concurrency and its implementation as many-core dynamic RISC processors. - Thomas A. M. Bernard; Kostas Bousias; Liang Guang; Chris R. Jesshope; Mike Lankamp; Michiel W. van Tol; Li Zhang 034 (ICSAMOS, 2008)

Evaluating CMPs and Their Memory Architecture. - Chris R. Jesshope; Mike Lankamp; Li Zhang 034 (ARCS, 2009)

Making multi-cores mainstream - from security to scalability. - Chris R. Jesshope; Michael A. Hicks 001; Mike Lankamp; Raphael 'kena' Poss; Li Zhang 034 (PARCO, 2009)

Implementation and evaluation of a microthread architecture. - Kostas Bousias; Liang Guang; Chris R. Jesshope; Mike Lankamp (J. Syst. Archit., 2009)

An implementation of the SANE Virtual Processor using POSIX threads. - Michiel W. van Tol; Chris R. Jesshope; Mike Lankamp; Simon Polstra (J. Syst. Archit., 2009)

The implementation of an SVP many-core processor and the evaluation of its memory architecture. - Chris R. Jesshope; Mike Lankamp; Li Zhang 034 (SIGARCH Comput. Archit. News, 2009)

Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. - Raphael Poss; Mike Lankamp; Qiang Yang 006; Jian Fu; Michiel W. van Tol; Chris R. Jesshope (DSD, 2012)

Heterogeneous integration to simplify many-core architecture simulations. - Raphael Poss; Mike Lankamp; Muhammad Irfan Uddin; Jaroslav Sykora; Leos Kafka (RAPIDO, 2012)

MGSim - A simulation environment for multi-core research and education. - Raphael Poss; Mike Lankamp; Qiang Yang 006; Jian Fu; Muhammad Irfan Uddin; Chris R. Jesshope (ICSAMOS, 2013)

MGSim - Simulation tools for multi-core processor architectures - Mike Lankamp; Raphael 'kena' Poss; Qiang Yang 006; Jian Fu; Muhammad Irfan Uddin; Chris R. Jesshope (CoRR, 2013)

Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management. - Raphael Poss; Mike Lankamp; Qiang Yang 006; Jian Fu; Michiel W. van Tol; Muhammad Irfan Uddin; Chris R. Jesshope (Microprocess. Microsystems, 2013)