Understanding software approaches for GPGPU reliability. - Martin Dimitrov; Mike Mantor; Huiyang Zhou (GPGPU, 2009)

Accelerating MATLAB Image Processing Toolbox functions on GPUs. - Jingfei Kong; Martin Dimitrov; Yi Yang 018; Janaka Liyanage; Lin Cao; Jacob Staples; Mike Mantor; Huiyang Zhou (GPGPU, 2010)

Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing. - Ping Xiang; Yi Yang 018; Mike Mantor; Norm Rubin; Huiyang Zhou (PACT, 2012)

Shared memory multiplexing: a novel way to improve GPGPU throughput. - Yi Yang 018; Ping Xiang; Mike Mantor; Norm Rubin; Huiyang Zhou (PACT, 2012)

AMD Radeon™ HD 7970 with graphics core next (GCN) architecture. - Mike Mantor (Hot Chips Symposium, 2012)

CPU-assisted GPGPU on fused CPU-GPU architectures. - Yi Yang 018; Ping Xiang; Mike Mantor; Huiyang Zhou (HPCA, 2012)

Fixing Performance Bugs: An Empirical Study of Open-Source GPGPU Programs. - Yi Yang 018; Ping Xiang; Mike Mantor; Huiyang Zhou (ICPP, 2012)

A unified optimizing compiler framework for different GPGPU architectures. - Yi Yang 018; Ping Xiang; Jingfei Kong; Mike Mantor; Huiyang Zhou (ACM Trans. Archit. Code Optim., 2012)

Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement. - Ping Xiang; Yi Yang 018; Mike Mantor; Norm Rubin; Lisa R. Hsu; Huiyang Zhou (ICS, 2013)

A Case for a Flexible Scalar Unit in SIMT Architecture. - Yi Yang 018; Ping Xiang; Michael Mantor; Norman Rubin; Lisa R. Hsu; Qunfeng Dong; Huiyang Zhou (IPDPS, 2014)

Kabini: An AMD Accelerated Processing Unit System on A Chip. - Dan Bouvier; Brad Cohen; Walter Fry; Sreekanth Godey; Michael Mantor (IEEE Micro, 2014)

Revisiting ILP Designs for Throughput-Oriented GPGPU Architecture. - Ping Xiang; Yi Yang 018; Mike Mantor; Norm Rubin; Huiyang Zhou (CCGRID, 2015)

A model-driven approach to warp/thread-block level GPU cache bypassing. - Hongwen Dai; Chao Li 004; Huiyang Zhou; Saurabh Gupta 002; Christos Kartsaklis; Mike Mantor (DAC, 2016)

GPU Performance vs. Thread-Level Parallelism: Scalability Analysis and a Novel Way to Improve TLP. - Zhen Lin; Michael Mantor; Huiyang Zhou (ACM Trans. Archit. Code Optim., 2018)

7NM "NAVI" GPU - A GPU Built for Performance and Efficiency. - Mike Mantor (Hot Chips Symposium, 2019)

Coordinated CTA Combination and Bandwidth Partitioning for GPU Concurrent Kernel Execution. - Zhen Lin; Hongwen Dai; Michael Mantor; Huiyang Zhou (ACM Trans. Archit. Code Optim., 2019)

Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. - Alan Smith 003; Gabriel H. Loh; Michael J. Schulte; Mike Ignatowski; Samuel Naffziger; Mike Mantor; Nathan Kalyanasundharam; Vamsi Alla; Nicholas Malaya; Joseph L. Greathouse; Eric Chapman; Raja Swaminathan (ISCA, 2024)