A microprogramming language for the B-1726. - David J. DeWitt; Michael S. Schlansker; Daniel E. Atkins (MICRO, 1973)

Systematically derived instruction sets for high-level language support. - Pradip Bose; B. Ramakrishna Rau; Michael S. Schlansker (ACM Southeast Regional Conference, 1982)

The Cydram 5 Stride-Insensitive Memory System. - B. Ramakrishna Rau; Michael S. Schlansker; David W. L. Yen (ICPP (1), 1989)

Parallelization of loops with exits on pipelined architectures. - Parthasarathy P. Tirumalai; Meng Lee; Michael S. Schlansker (SC, 1990)

Parallelization of WHILE loops on pipelined architectures. - Parthasarathy P. Tirumalai; Meng Lee; Michael S. Schlansker (J. Supercomput., 1991)

Sentinel Scheduling for VLIW and Superscalar Processors. - Scott A. Mahlke; William Y. Chen; Wen-mei W. Hwu; B. Ramakrishna Rau; Michael S. Schlansker (ASPLOS, 1992)

Code generation schema for modulo scheduled loops. - B. Ramakrishna Rau; Michael S. Schlansker; Parthasarathy P. Tirumalai (MICRO, 1992)

Register Allocation for Software Pipelined Loops. - B. Ramakrishna Rau; Meng Lee; Parthasarathy P. Tirumalai; Michael S. Schlansker (PLDI, 1992)

Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. - Michael S. Schlansker; Vinod Kathail (LCPC, 1993)

Sentinel Scheduling for VLIW and Superscalar Processors. - Scott A. Mahlke; William Y. Chen; Roger A. Bringmann; Richard E. Hank; Wen-mei W. Hwu; B. Ramakrishna Rau; Michael S. Schlansker (ACM Trans. Comput. Syst., 1993)

Height reduction of control recurrences for ILP processors. - Michael S. Schlansker; Vinod Kathail; Sadun Anik (MICRO, 1994)

Spill-free parallel scheduling of basic blocks. - B. Natarajan; Michael S. Schlansker (MICRO, 1995)

Critical path reduction for scalar programs. - Michael S. Schlansker; Vinod Kathail (MICRO, 1995)

Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. - Chandra Chekuri; Richard Johnson; Rajeev Motwani 001; B. Natarajan; B. Ramakrishna Rau; Michael S. Schlansker (MICRO, 1996)

Global Predicate Analysis and Its Application to Register Allocation. - David M. Gillies; Roy Dz-Ching Ju; Richard Johnson; Michael S. Schlansker (MICRO, 1996)

Analysis Techniques for Predicated Code. - Richard Johnson; Michael S. Schlansker (MICRO, 1996)

Parallelization of Control Recurrences for ILP Processors. - Michael S. Schlansker; Vinod Kathail; Sadun Anik (Int. J. Parallel Program., 1996)

Challenges to Combining General-Purpose and Multimedia Processors. - Thomas M. Conte; Pradeep K. Dubey; Matthew D. Jennings; Ruby B. Lee; Alex Peleg; Salliah Rathnam; Michael S. Schlansker; Peter Song; Andrew Wolfe (Computer, 1997)

Compilers for Instruction-Level Parallelism. - Michael S. Schlansker; Thomas M. Conte; James C. Dehnert; Kemal Ebcioglu; Jesse Zhixi Fang; Carol L. Thompson (Computer, 1997)

Techniques for critical path reduction of scalar programs. - Michael S. Schlansker; Vinod Kathail (Int. J. Parallel Program., 1997)

Control CPR: A Branch Height Reduction Optimization for EPIC Architectures. - Michael S. Schlansker; Scott A. Mahlke; Richard Johnson (PLDI, 1999)

Embedded Computing: New Directions in Architecture and Automation. - B. Ramakrishna Rau; Michael S. Schlansker (HiPC, 2000)

EPIC: Explicititly Parallel Instruction Computing. - Michael S. Schlansker; B. Ramakrishna Rau (Computer, 2000)

ShiftQ: a bufferred interconnect for custom loop accelerators. - Shail Aditya; Michael S. Schlansker (CASES, 2001)

Embedded Computer Architecture and Automation. - B. Ramakrishna Rau; Michael S. Schlansker (Computer, 2001)

Guest Editors' Introduction. - Michael S. Schlansker; Chris J. Newburn (J. Instr. Level Parallelism, 2001)

Compiling for EPIC architectures. - Vinod Kathail; Michael S. Schlansker; B. Ramakrishna Rau (Proc. IEEE, 2001)

Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. - Scott A. Mahlke; Rajiv A. Ravindran; Michael S. Schlansker; Robert Schreiber; Timothy Sherwood (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

In Memory of Bob Rau. - Michael S. Schlansker (MICRO, 2003)

A Distributed Control Path Architecture for VLIW Processors. - Hongtao Zhong; Kevin Fan; Scott A. Mahlke; Michael S. Schlansker (IEEE PACT, 2005)

Fast synchronization for chip multiprocessors. - Jack Sampson; Rubén González; Jean-Francois Collard; Norman P. Jouppi; Michael S. Schlansker (SIGARCH Comput. Archit. News, 2005)

Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. - Jack Sampson; Rubén González; Jean-Francois Collard; Norman P. Jouppi; Michael S. Schlansker; Brad Calder (MICRO, 2006)

High-performance ethernet-based communications for future multi-core processors. - Michael S. Schlansker; Nagabhushan Chitlur; Erwin Oertli; Paul M. Stillwell Jr.; Linda Rankin; Dennis Bradford; Richard J. Carter; Jayaram Mudigonda; Nathan L. Binkert; Norman P. Jouppi (SC, 2007)

Hash-based routing for scalable datacenters. - Mike Schlansker; Jean Tourrilhes; Yoshio Turner; Jose Renato Santos (ANCS, 2009)

Ensemble routing for datacenter networks. - Mike Schlansker; Yoshio Turner; Jean Tourrilhes; Alan Karp (ANCS, 2010)

Killer Fabrics for Scalable Datacenters. - Mike Schlansker; Jean Tourrilhes; Yoshio Turner; Jose Renato Santos (ICC, 2010)

Routing Optimization for Ensemble Routing. - Wenfei Wu; Yoshio Turner; Mike Schlansker (ANCS, 2011)

Cydra 5. - Michael S. Schlansker (Encyclopedia of Parallel Computing, 2011)

CORONET: Fault tolerance for Software Defined Networks. - Hyojoon Kim; Mike Schlansker; Jose Renato Santos; Jean Tourrilhes; Yoshio Turner; Nick Feamster (ICNP, 2012)

Configurable optical interconnects for scalable datacenters. - Michael S. Schlansker; Michael R. T. Tan; Jean Tourrilhes; Jose Renato Santos; Shih-Yuan Wang (OFC/NFOEC, 2013)

Enabling Topological Flexibility for Data Centers Using OmniSwitch. - Yiting Xia; Mike Schlansker; T. S. Eugene Ng; Jean Tourrilhes (HotCloud, 2015)

The 2014 MICRO Test of Time Award Winners: From 1978 to 1992. - Onur Mutlu; Rich Belgard; Nick Tredennick; Mike Schlansker (IEEE Micro, 2016)

Design Challenges for High Performance, Scalable NFV Interconnects. - Guyue Liu; K. K. Ramakrishnan; Mike Schlansker; Jean Tourrilhes; Timothy Wood 001 (KBNets@SIGCOMM, 2017)