A subsampling UWB radio architecture by analytic signaling. - Mike Shuo-Wei Chen; Robert W. Brodersen (ICASSP (4), 2004)

Future wireless systems: UWB, 60GHz, and cognitive radios. - Danijela Cabric; Mike Shuo-Wei Chen; David A. Sobel; Jing Yang 004; Robert W. Brodersen (CICC, 2005)

A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling. - Mike Shuo-Wei Chen; Robert W. Brodersen (IEICE Trans. Electron., 2005)

Digital Complex Signal Processing Techniques for Impulse Radio. - Mike Shuo-Wei Chen; Robert W. Brodersen (GLOBECOM, 2006)

A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOS. - Mike Shuo-Wei Chen; Robert W. Brodersen (ISSCC, 2006)

Novel Radio Architectures for UWB, 60 GHz, and Cognitive Wireless Systems. - Danijela Cabric; Mike Shuo-Wei Chen; David A. Sobel; Stanley Wang; Jing Yang 004; Robert W. Brodersen (EURASIP J. Wirel. Commun. Netw., 2006)

A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$ mu{ hbox{m}}$ CMOS. - Shuo-Wei Michael Chen; Robert W. Brodersen (IEEE J. Solid State Circuits, 2006)

Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications. - Andrew Fort; Mike Shuo-Wei Chen; Robert W. Brodersen; Claude Desset; Piet Wambacq; Leo Van Biesen (ICC, 2007)

A Subsampling Radio Architecture for Ultrawideband Communications. - Shuo-Wei Michael Chen; Robert W. Brodersen (IEEE Trans. Signal Process., 2007)

A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. - Lalitkumar Nathawad; Masoud Zargari; Hirad Samavati; Srenik S. Mehta; Alireza Kheirkhahi; Phoebe Chen; Ke Gong; Babak Vakili-Amini; Justin A. Hwang; Mike Shuo-Wei Chen; Manolis Terrovitis; Brian J. Kaczynski; et al. (ISSCC, 2008)

A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. - Masoud Zargari; Lalitkumar Nathawad; Hirad Samavati; Srenik S. Mehta; Alireza Kheirkhahi; Phoebe Chen; Ke Gong; Babak Vakili-Amini; Justin A. Hwang; Mike Shuo-Wei Chen; Manolis Terrovitis; Brian J. Kaczynski; et al. (IEEE J. Solid State Circuits, 2008)

Design and implementation of a CMO 802.11n SoC. - Sundar G. Sankaran; Brian J. Zargari; Lalitkumar Nathawad; Hirad Samavati; Srenik S. Mehta; Alireza Kheirkhahi; Phoebe Chen; Ke Gong; Babak Vakili-Amini; Justin A. Hwang; Mike Shuo-Wei Chen; Manolis Terrovitis; et al. (IEEE Commun. Mag., 2009)

A calibration-free 800MHz fractional-N digital PLL with embedded TDC. - Mike Shuo-Wei Chen; David K. Su; Srenik S. Mehta (ISSCC, 2010)

A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC. - Mike Shuo-Wei Chen; David K. Su; Srenik S. Mehta (IEEE J. Solid State Circuits, 2010)

A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC. - Shahram Abdollahi-Alibeik; David Weber; Hakan Dogan; William W. Si; Burcin Baytekin; Abbas Komijani; Richard Chang 003; Babak Vakili-Amini; MeeLan Lee; Haitao Gan; Yashar Rajavi; Hirad Samavati; et al. (ISSCC, 2011)

A non-uniform sampling ADC architecture with embedded alias-free asynchronous filter. - Dylan Hand; Mike Shuo-Wei Chen (GLOBECOM, 2012)

Overhead minimization techniques for digital phase-locked loop frequency synthesizer. - Mike Shuo-Wei Chen (MWSCAS, 2012)

A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS. - Jae-Won Nam; David Chiong; Mike Shuo-Wei Chen (CICC, 2013)

A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS. - Praveen Kumar Sharma; Mike Shuo-Wei Chen (CICC, 2013)

A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS. - Shiyu Su; Tu-I Tsai; Praveen Kumar Sharma; Mike Shuo-Wei Chen (VLSIC, 2014)

Cross-Layer Modeling and Simulation of Circuit Reliability. - Yu Cao 001; Jyothi Velamala; Ketul Sutaria; Mike Shuo-Wei Chen; Jonathan Ahlbin; Ivan Sanchez Esqueda; Michael Bajura; Michael Fritze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS. - Tzu-Fan Wu; Cheng-Ru Ho; Mike Shuo-Wei Chen (CICC, 2015)

A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. - Shiyu Su; Tu-I Tsai; Praveen Kumar Sharma; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2015)

Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS. - Cheng-Ru Ho; Mike Shuo-Wei Chen (ESSCIRC, 2016)

10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. - Cheng-Ru Ho; Mike Shuo-Wei Chen (ISSCC, 2016)

27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS. - Shiyu Su; Mike Shuo-Wei Chen (ISSCC, 2016)

A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. - Jae-Won Nam; Mohsen Hassanpourghadi; Aoyang Zhang; Mike Shuo-Wei Chen (VLSI Circuits, 2016)

A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS. - Cheng-Ru Ho; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2016)

A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS. - Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2016)

A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme. - Cheng-Ru Ho; Mike Shuo-Wei Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS. - Jae-Won Nam; Mike Shuo-Wei Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter. - Tzu-Fan Wu; Sourya Dey; Mike Shuo-Wei Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A time multiplexed network architecture for large-scale neuromorphic computing. - Rezwan A. Rasul; Pedram Teimouri; Mike Shuo-Wei Chen (MWSCAS, 2017)

A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter. - Tzu-Fan Wu; Cheng-Ru Ho; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2017)

A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS. - Mohsen Hassanpourghadi; Praveen Kumar Sharma; Mike Shuo-Wei Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Evolutions of SAR ADC: From high resolution to high speed regime. - Mike Shuo-Wei Chen (CICC, 2018)

A 200MHz-BW 0.13mm2 62dB-DR VCO-based non-uniform sampling ADC with phase-domain level crossing in 65nm CMOS. - Tzu-Fan Wu; Mike Shuo-Wei Chen (CICC, 2018)

A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling. - Cheng-Ru Ho; Mike Shuo-Wei Chen (ISSCC, 2018)

A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. - Cheng-Ru Ho; Mike Shuo-Wei Chen (ISSCC, 2018)

A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands. - Shiyu Su; Mike Shuo-Wei Chen (ISSCC, 2018)

A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency. - Aoyang Zhang; Mike Shuo-Wei Chen (VLSI Circuits, 2018)

A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. - Jae-Won Nam; Mohsen Hassanpourghadi; Aoyang Zhang; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2018)

A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands. - Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2018)

A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells. - Mohsen Hassanpourghadi; Mike Shuo-Wei Chen (CICC, 2019)

A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS. - Jae-Won Nam; Mike Shuo-Wei Chen (CICC, 2019)

A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency. - Aoyang Zhang; Mike Shuo-Wei Chen (ISSCC, 2019)

A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM. - Shiyu Su; Mike Shuo-Wei Chen (VLSI Circuits, 2019)

A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing. - Tzu-Fan Wu; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2019)

A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement. - Aoyang Zhang; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2019)

A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier. - Aoyang Zhang; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2019)

Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. - Juzheng Liu; Mohsen Hassanpourghadi; Qiaochu Zhang; Shiyu Su; Mike Shuo-Wei Chen (ICCAD, 2020)

CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. - Qiaochu Zhang; Shiyu Su; Juzheng Liu; Mike Shuo-Wei Chen (ICCAD, 2020)

10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. - Shiyu Su; Mike Shuo-Wei Chen (ISSCC, 2020)

16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS. - Tzu-Fan Wu; Mike Shuo-Wei Chen (ISSCC, 2020)

A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer. - Jae-Won Nam; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2020)

A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application. - Rezwan A. Rasul; Mike Shuo-Wei Chen (CICC, 2021)

A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement. - Aoyang Zhang; Mostafa M. Ayesh; Soumya Mahapatra; Mike Shuo-Wei Chen (CICC, 2021)

Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. - Mohsen Hassanpourghadi; Shiyu Su; Rezwan A. Rasul; Juzheng Liu; Qiaochu Zhang; Mike Shuo-Wei Chen (DAC, 2021)

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. - Juzheng Liu; Shiyu Su; Meghna Madhusudan; Mohsen Hassanpourghadi; Samuel Saunders; Qiaochu Zhang; Rezwan A. Rasul; Yaguang Li; Jiang Hu; Arvind Kumar Sharma; Sachin S. Sapatnekar; Ramesh Harjani; et al. (ICCAD, 2021)

Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. - Mike Shuo-Wei Chen; Wei-Zen Chen; Amir Amirkhany (ISSCC, 2021)

29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. - Qiaochu Zhang; Shiyu Su; Cheng-Ru Ho; Mike Shuo-Wei Chen (ISSCC, 2021)

26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency. - Aoyang Zhang; Ce Yang; Mostafa M. Ayesh; Mike Shuo-Wei Chen (ISSCC, 2021)

A Time-Approximation Filter for Direct RF Transmitter. - Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2021)

A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis. - Mohsen Hassanpourghadi; Rezwan A. Rasul; Mike Shuo-Wei Chen (ACM Trans. Design Autom. Electr. Syst., 2021)

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. - Shiyu Su; Qiaochu Zhang; Mohsen Hassanpourghadi; Juzheng Liu; Rezwan A. Rasul; Mike Shuo-Wei Chen (ASP-DAC, 2022)

TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. - Shiyu Su; Qiaochu Zhang; Juzheng Liu; Mohsen Hassanpourghadi; Rezwan A. Rasul; Mike Shuo-Wei Chen (ASP-DAC, 2022)

High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range. - Shiyu Su; Mike Shuo-Wei Chen (CICC, 2022)

A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. - Qiaochu Zhang; Shiyu Su; Mike Shuo-Wei Chen (DAC, 2022)

A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology. - Juzheng Liu; Mohsen Hassanpourghadi; Mike Shuo-Wei Chen (ISSCC, 2022)

Non-Uniform Sampling Data Converters: A Journey to Uncharted Circuits and Systems. - Mike Shuo-Wei Chen (VLSI-DAT, 2022)

A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC. - Juzheng Liu; Mohsen Hassanpourghadi; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2022)

SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter. - Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2022)

A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. - Qiaochu Zhang; Shiyu Su; Cheng-Ru Ho; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2022)

A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. - Hsiang-Chun Cheng; Shiyu Su; Mayank Palaria; Qiaochu Zhang; Ce Yang; Sushmit Hossain; Ryan M. Bena; Buyun Chen; Zerui Liu; Juzheng Liu; Rezwan A. Rasul; Quan Nguyen 004; et al. (CICC, 2023)

A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. - Shiyu Su; Qiaochu Zhang; Mike Shuo-Wei Chen (CICC, 2023)

Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. - Mayank Palaria; Shiyu Su; Hsiang-Chun Cheng; Rezwan A. Rasul; Qiaochu Zhang; Soumya Mahapatra; Chong-Fatt Law; Sushmit Hossain; Ryan M. Bena; Wei Wu; Quan Nguyen 004; Mike Shuo-Wei Chen (ESSCIRC, 2023)

A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. - Qiaochu Zhang; Hsiang-Chun Cheng; Shiyu Su; Mike Shuo-Wei Chen (ISSCC, 2023)

Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter. - Ce Yang; Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2023)

A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. - Mutian Zhu; Mohsen Hassanpourghadi; Qiaochu Zhang; Mike Shuo-Wei Chen; Anthony F. J. Levi; Sandeep Gupta 001 (DATE, 2024)

5.3 A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS. - Mostafa M. Ayesh; Soumya Mahapatra; Ce Yang; Mike Shuo-Wei Chen (ISSCC, 2024)

A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS. - Juzheng Liu; Ayman Shabra; Stacy Ho; Gabriele Manganaro; Mike Shuo-Wei Chen (VLSI Technology and Circuits, 2024)

Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET. - Qiaochu Zhang; Shiyu Su; Baishakhi Rani Biswas; Sandeep Gupta 001; Mike Shuo-Wei Chen (VLSI Technology and Circuits, 2024)

A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. - Qiaochu Zhang; Shiyu Su; Zerui Liu; Hsiang-Chun Cheng; Zhengyi Qiu; Mayank Palaria; Jiacheng Ye; Deming Meng; Buyun Chen; Sushmit Hossain; Wei Wu; Mike Shuo-Wei Chen (VLSI Technology and Circuits, 2024)

Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). - Mike Shuo-Wei Chen; Visvesh S. Sathe 001; Massimo Alioto; Jae-Sun Seo; Hidehiro Shiga (IEEE J. Solid State Circuits, 2024)

Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. - Qiaochu Zhang; Hsiang-Chun Cheng; Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2024)

A Blocker-Tolerant Non-Uniform Sub-Sampling Receiver With a Non-Uniform Discrete-Time FIR Filter. - Mostafa M. Ayesh; Soumya Mahapatra; Ce Yang; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2024)

26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS. - Soumya Mahapatra; Mostafa M. Ayesh; Ce Yang; Mayank Palaria; Shiyu Su; Aoyang Zhang; Mike Shuo-Wei Chen (ISSCC, 2025)

11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS. - Ce Yang; Shiyu Su; Mostafa M. Ayesh; Soumya Mahapatra; Maysara Hamada; Vinay Chenna; Hossein Hashemi 001; Mike Shuo-Wei Chen (ISSCC, 2025)

Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adders. - Shiyu Su; Qiaochu Zhang; Baishakhi Rani Biswas; Sandeep K. Gupta 001; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2025)