Designing a virtual runtime for FPGA accelerators in the cloud. - Mikhail Asiatici; Nithin George; Kizheppatt Vipin; Suhaib A. Fahmy; Paolo Ienne (FPL, 2016)

Virtualized Execution Runtime for FPGA Accelerators in the Cloud. - Mikhail Asiatici; Nithin George; Kizheppatt Vipin; Suhaib A. Fahmy; Paolo Ienne (IEEE Access, 2017)

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only). - Mikhail Asiatici; Damian Maiorano; Paolo Ienne (FPGA, 2018)

LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). - Andrea Guerrieri; Sahand Kashani-Akhavan; Mikhail Asiatici; Pasquale Lombardi; Bilel Belhadj; Paolo Ienne (FPGA, 2018)

Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires. - Miku J. Laakso; Simon J. Bleiker; Jessica Liljeholm; Gustaf E. Martensson; Mikhail Asiatici; Andreas C. Fischer; Göran Stemme; Thorbjorn Ebefors; Frank Niklaus (IEEE Access, 2018)

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. - Mikhail Asiatici; Paolo Ienne (FPGA, 2019)

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. - Mikhail Asiatici; Paolo Ienne (FPL, 2019)

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. - Gabor Csordas; Mikhail Asiatici; Paolo Ienne (FPT, 2019)

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips. - Andrea Guerrieri; Sahand Kashani-Akhavan; Mikhail Asiatici; Paolo Ienne (IEEE Access, 2019)

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. - Mikhail Asiatici; Damian Maiorano; Paolo Ienne (ASAP, 2020)

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. - Mikhail Asiatici; Paolo Ienne (ISCA, 2021)

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System. - Mikhail Asiatici; Damian Maiorano; Paolo Ienne (J. Signal Process. Syst., 2021)

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities. - Mikhail Asiatici (2021)

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs. - Mikhail Asiatici; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2022)