A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. - Koichi Nose; Mikihiro Kajita; Masayuki Mizuno (ISSCC, 2006)

A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. - Koichi Nose; Mikihiro Kajita; Masayuki Mizuno (IEEE J. Solid State Circuits, 2006)

A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. - Shunichi Kaeriyama; Mikihiro Kajita; Masayuki Mizuno (ISSCC, 2007)

A method using circuit/substrate macro modeling to analyze substrate noise in a 3.2-GHz 350M-transistor microprocessor. - Mikiko Sode Tanaka; Mikihiro Kajita; Naoya Nakayama; Satoshi Nakamoto (CICC, 2008)

Full Chip Circuit/Substrate Macro Modeling Method Which Controls the Analysis Accuracy and CPU Time by Using Current Density. - Mikiko Sode Tanaka; Mikihiro Kajita; Naoya Nakayama; Satoshi Nakamoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. - Shunichi Kaeriyama; Mikihiro Kajita; Masayuki Mizuno (IEICE Trans. Electron., 2011)