A method for compensating the D/A converter frequency response distortion in OFDM system. - Olli Väänänen; Mikko Kaltiokallio; Jouko Vankka; Kari Halonen (ECCTD, 2005)

Analysis of different feedback topologies to LNA input matching. - Mikko Kaltiokallio; Jouni Kaukovuori; Jussi Ryynänen (ECCTD, 2007)

Design of Precise Gain GmC-leapfrog Filters. - Mikko Kaltiokallio; Saska Lindfors; Ville Saari; Jussi Ryynänen (ISCAS, 2007)

A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver. - Ville Saari; Mikko Kaltiokallio; Saska Lindfors; Jussi Ryynänen; Kari Halonen (ISSCC, 2007)

A WiMedia UWB receiver with a synthesizer. - Mikko Kaltiokallio; Ville Saari; Tapio Rapinoja; Kari Stadius; Jussi Ryynänen; Saska Lindfors; Kari Halonen (ESSCIRC, 2008)

Analysis and design of common-gate low-noise amplifier for wideband applications. - Jouni Kaukovuori; Mikko Kaltiokallio; Jussi Ryynänen (Int. J. Circuit Theory Appl., 2009)

A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for a UWB Radio Receiver. - Ville Saari; Mikko Kaltiokallio; Saska Lindfors; Jussi Ryynänen; Kari Halonen (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Active polyphase filter analysis. - Mikko Kaltiokallio; Jussi Ryynänen; Saska Lindfors (ISCAS, 2010)

Wideband 2 to 6GHz RF front-end with blocker filtering. - Mikko Kaltiokallio; Ville Saari; Jussi Ryynänen; Sami Kallioinen; Aarno Pärssinen (ESSCIRC, 2011)

A 0.7 - 2.6 GHz high-linearity rf front-end for cognitive radio spectrum sensing. - Kari Stadius; Mikko Kaltiokallio; Jussi Ollikainen; Tuomas Parnanen; Ville Saari; Jussi Ryynänen (ISCAS, 2011)

Wideband 2 to 6 GHz RF Front-End With Blocker Filtering. - Mikko Kaltiokallio; Ville Saari; Sami Kallioinen; Aarno Pärssinen; Jussi Ryynänen (IEEE J. Solid State Circuits, 2012)

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS. - Markus Hiienkari; Jukka Teittinen; Lauri Koskinen; Matthew J. Turnquist; Mikko Kaltiokallio (CICC, 2014)

A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator. - Mikko Englund; Kim B. Ostman; Olli Viitala; Mikko Kaltiokallio; Kari Stadius; Jussi Ryynänen; Kimmo Koli (ESSCIRC, 2014)

28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS. - Mikko Englund; Kim B. Östman; Olli Viitala; Mikko Kaltiokallio; Kari Stadius; Kimmo Koli; Jussi Ryynänen (ISSCC, 2014)

A 0.8-3 GHz mixer-first receiver with on-chip transformer balun in 65-nm CMOS. - Tero Tikka; Kari Stadius; Jussi Ryynänen; Mikko Kaltiokallio (ESSCIRC, 2015)

A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS. - Mikko Englund; Kim B. Ostman; Olli Viitala; Mikko Kaltiokallio; Kari Stadius; Kimmo Koli; Jussi Ryynänen (IEEE J. Solid State Circuits, 2015)

Analysis and Design of N-Path Filter Offset Tuning in a 0.7-2.7-GHz Receiver Front-End. - Kim B. Ostman; Mikko Englund; Olli Viitala; Mikko Kaltiokallio; Kari Stadius; Kimmo Koli; Jussi Ryynänen (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)