A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Vijaykrishnan Narayanan (FPT, 2004)

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. - Vivek Garg; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001 (ASP-DAC, 2005)

A function generator-based reconfigurable system. - Vivek Garg; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001 (ASP-DAC, 2005)

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Narayanan Vijaykrishnan (ASP-DAC, 2005)

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Narayanan Vijaykrishnan (FPGA, 2005)

Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Narayanan Vijaykrishnan (IPDPS, 2005)

Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Narayanan Vijaykrishnan (VLSI Design, 2005)

An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. - Vivek Garg; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001 (VLSI Design, 2006)