A 480-MHz RISC microprocessor in a 0.12-μm Leff CMOS technology with copper interconnects. - Chekib Akrout; John Bialas; Miles G. Canada; Duane Cawthron; James Corr; Bijan Davari; Robert Floyd 002; Stephen F. Geissler; Ronald Goldblatt; Robert Houle; Paul Kartschoke; Diane Kramer; et al. (IEEE J. Solid State Circuits, 1998)

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features. - Norman J. Rohrer; Cédric Lichtenau; Peter A. Sandon; Paul Kartschoke; Erwin B. Cohen; Miles G. Canada; Thomas Pflüger; Mathew I. Ringler; Rolf B. Hilgendorf; Stephen F. Geissler; Jeffrey S. Zimmerman (IEEE J. Solid State Circuits, 2005)

A 64B CPU Pair: Dual- and Single-Processor Chips. - Erwin B. Cohen; Norman J. Rohrer; Peter A. Sandon; Miles G. Canada; Cédric Lichtenau; Mathew I. Ringler; Paul Kartschoke; Robert Floyd 002; Jan Heaslip; M. Ross; Thomas Pflueger; Rolf B. Hilgendorf; et al. (ISSCC, 2006)

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. - Jürgen Pille; Dieter F. Wendel; Otto Wagner; Rolf Sautter; Wolfgang Penth; Thomas Fröhnel; Stefan Büttner; Otto A. Torreiter; Martin Eckert; Jose Paredes; David Hrusecky; David Ray; et al. (ISSCC, 2010)