Eadix l6 evaluation of some elementary functions. - Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1972)

Radix-16 Evaluation of Certain Elementary Functions. - Milos D. Ercegovac (IEEE Trans. Computers, 1973)

A general method for evaluation of functions and computations in a digital computing. - Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1975)

A General Method for Evaluation of Functions and Computations in A Digital Computer - Milos D. Ercegovac (1975)

A General Hardware-Oriented Method for Evaluation of Functions and Computations in a Digital Computer. - Milos D. Ercegovac (IEEE Trans. Computers, 1977)

On-Line Algorithms for Division and Multiplication. - Kishor S. Trivedi; Milos D. Ercegovac (IEEE Trans. Computers, 1977)

An on-line square rooting algorithm. - Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1978)

An arithmetic module for efficient evaluation of functions. - Milos D. Ercegovac; Melvin M. Takata (IEEE Symposium on Computer Arithmetic, 1978)

Design of a digit-slice on-line arithmetic unit. - Abdolali Gorji-Sinaki; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1981)

A simulator for on-line arithmetic. - Cauligi S. Raghavendra; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1981)

Floating-point on-line arithmetic: Algorithms. - Osaaki Watanuki; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1981)

Floating-point on-line arithmetic: Error analysis. - Osaaki Watanuki; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1981)

Queue machines: an organization for parallel computation. - M. Feller; Milos D. Ercegovac (CONPAR, 1981)

A scheme for handling arrays in data-flow systems. - Jean-Luc Gaudiot; Milos D. Ercegovac (ICDCS, 1982)

A On-Line Square Root Algorithm. - Vojin G. Oklobdzija; Milos D. Ercegovac (IEEE Trans. Computers, 1982)

A higher-radix division with simple selection of quotient digits. - Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1983)

On-line multiplicative normalization. - Aksenti L. Grnarov; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1983)

Error Analysis of Certain Floating-Point On-Line Algorithms. - Osaaki Watanuki; Milos D. Ercegovac (IEEE Trans. Computers, 1983)

Performance Analysis of a Data-Flow Computer with Variable Resolution Actors. - Jean-Luc Gaudiot; Milos D. Ercegovac (ICDCS, 1984)

Fault Tolerance in Binary Tree Architectures. - Cauligi S. Raghavendra; Algirdas Avizienis; Milos D. Ercegovac (IEEE Trans. Computers, 1984)

A division algorithm with prediction of quotient digits. - Milos D. Ercegovac; Tomás Lang (IEEE Symposium on Computer Arithmetic, 1985)

A functional language for description and design of digital systems: sequential constructs. - F. Meshkinpour; Milos D. Ercegovac (DAC, 1985)

vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms. - Dorab Patel; Martine D. F. Schlag; Milos D. Ercegovac (FPCA, 1985)

Performance evaluation of a simulated data-flow computer with low-resolution actors. - Jean-Luc Gaudiot; Milos D. Ercegovac (J. Parallel Distributed Comput., 1985)

A radix-4 on-line division algorithm. - Paul K.-G. Tu; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1987)

On-the-Fly Conversion of Redundant into Conventional Representations. - Milos D. Ercegovac; Tomás Lang (IEEE Trans. Computers, 1987)

Implementation of fast radix-4 division with operands scaling. - Milos D. Ercegovac; Tomás Lang; Ramin Modiri (ICCD, 1988)

On-Line Scheme for Computing Rotation Factors. - Milos D. Ercegovac; Tomás Lang (J. Parallel Distributed Comput., 1988)

Heterogeneity in supercomputer architectures. - Milos D. Ercegovac (Parallel Comput., 1988)

Design of an on-line multiply-add module for recursive digital filters. - Ralph Hans Brackert Jr.; Milos D. Ercegovac; Alan N. Willson Jr. (IEEE Symposium on Computer Arithmetic, 1989)

On-the-fly rounding for division and square root. - Milos D. Ercegovac; Tomás Lang (IEEE Symposium on Computer Arithmetic, 1989)

Design of on-line division unit. - Paul K.-G. Tu; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1989)

A Modeling Methodology for the Analysis of Concurrent Systems and Computations. - Alex Kapelnikov; Richard R. Muntz; Milos D. Ercegovac (J. Parallel Distributed Comput., 1989)

Architectural Support for the Management of Tightly-Coupled Fine-Grain Goals in Flat Concurrent Prolog. - Leon Alkalaj; Tomás Lang; Milos D. Ercegovac (ISCA, 1990)

Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD. - Milos D. Ercegovac; Tomás Lang (IEEE Trans. Computers, 1990)

Radix-4 Square Root Without Initial PLA. - Milos D. Ercegovac; Tomás Lang (IEEE Trans. Computers, 1990)

Simple Radix-4 Division with Opterands Scaling. - Milos D. Ercegovac; Tomás Lang (IEEE Trans. Computers, 1990)

Fast Multiplication Without Carry-Propagate Addition. - Milos D. Ercegovac; Tomás Lang (IEEE Trans. Computers, 1990)

A novel CMOS implementation of double-edge-triggered flip-flops. - Shih-Lien Lu; Milos D. Ercegovac (IEEE J. Solid State Circuits, 1990)

Application of on-line arithmetic algorithms to the SVD computation: preliminary results. - Paul K.-G. Tu; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1991)

Module to Perform Multiplication, Division, and Square Root in Systolic Arrays for Matrix Computations. - Milos D. Ercegovac; Tomás Lang (J. Parallel Distributed Comput., 1991)

Gate array implementation of on-line algorithms for floating-point operations. - Paul K.-G. Tu; Milos D. Ercegovac (J. VLSI Signal Process., 1991)

Evaluation of two-summand adders implemented in ECDL CMOS differential logic. - Shih-Lien Lu; Milos D. Ercegovac (IEEE J. Solid State Circuits, 1991)

MAMACG: a tool for automatic mapping of matrix algorithms onto mesh array computational graphs. - Dinh Lê; Milos D. Ercegovac; Tomás Lang; Jaime H. Moreno (ASAP, 1992)

Variable Precision Representation for Efficient VQ Codebook Storage. - Raffi Dionysian; Milos D. Ercegovac (Data Compression Conference, 1992)

Architectural Support for Goal Management in Flat Concurrent Prolog. - Leon Alkalaj; Tomás Lang; Milos D. Ercegovac (Computer, 1992)

A methodology for performance analysis of parallel computations with looping constructs. - Alex Kapelnikov; Richard R. Muntz; Milos D. Ercegovac (J. Parallel Distributed Comput., 1992)

On-the-Fly Rounding. - Milos D. Ercegovac; Tomás Lang (IEEE Trans. Computers, 1992)

Very high radix division with selection by rounding and prescaling. - Milos D. Ercegovac; Tomás Lang; Paolo Montuschi (IEEE Symposium on Computer Arithmetic, 1993)

On digit-recurrence division implementations for field programmable gate arrays. - Marianne E. Louie; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1993)

Symbolic Synthesis of Parallel Processing Systems. - James J. Liu; Milos D. Ercegovac (IPPS, 1993)

ALIAS Environment: A Design Tool for Application Specific Arrays. - James J. Liu; Milos D. Ercegovac (SPDP, 1993)

Multiplication/ division/ square root module for massively parallel computers. - Milos D. Ercegovac; Tomás Lang (Integr., 1993)

Very-High Radix Division with Prescaling and Selection by Rounding. - Milos D. Ercegovac; Tomás Lang; Paolo Montuschi (IEEE Trans. Computers, 1994)

Conventional and on-line arithmetic designs for high-speed recursive digital filters. - John S. Fernando; Milos D. Ercegovac (J. VLSI Signal Process., 1994)

Implementing division with field programmable gate arrays. - Marianne E. Louie; Milos D. Ercegovac (J. VLSI Signal Process., 1994)

Sign detection and comparison networks with a small number of transitions. - Milos D. Ercegovac; Tomás Lang (IEEE Symposium on Computer Arithmetic, 1995)

A variable-precision square root implementation for field programmable gate arrays. - Marianne E. Louie; Milos D. Ercegovac (J. Supercomput., 1995)

Vector quantization with compressed codebooks. - Raffi Dionysian; Milos D. Ercegovac (Signal Process. Image Commun., 1996)

Vector quantization with variable-precision classification. - Raffi Dionysian; Milos D. Ercegovac (IEEE Trans. Image Process., 1996)

On recoding in arithmetic algorithms. - Milos D. Ercegovac; Tomás Lang (J. VLSI Signal Process., 1996)

Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size. - Alexandre F. Tenca; Milos D. Ercegovac (FPGA, 1997)

A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures. - Alexandre F. Tenca; Milos D. Ercegovac (FCCM, 1998)

Behavioral synthesis optimization using multiple precision arithmetic. - Milos D. Ercegovac; Darko Kirovski; George Mustafa; Miodrag Potkonjak (ICASSP, 1998)

Long and Fast Up/Down Counters. - Mircea R. Stan; Alexandre F. Tenca; Milos D. Ercegovac (IEEE Trans. Computers, 1998)

On the Design of High-Radix On-Line Division for Long Precision. - Alexandre F. Tenca; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 1999)

Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic. - Milos D. Ercegovac; Darko Kirovski; Miodrag Potkonjak (DAC, 1999)

FPGA-Based Structures for On-Line FFT and DCT. - Dannie Lau; Aaron Schneider; Milos D. Ercegovac; John D. Villasenor (FCCM, 1999)

BigSky-An On-Line Arithmetic Design Tool for FPGAs. - Aaron Schneider; Robert McIlhenny; Milos D. Ercegovac (FCCM, 2000)

A Component Framework for Communication in Distributed Applications. - Jeffrey M. Fischer; Milos D. Ercegovac (IPDPS, 2000)

Improving Goldschmidt Division, Square Root, and Square Root Reciprocal. - Milos D. Ercegovac; Laurent Imbert; David W. Matula; Jean-Michel Muller; Guoheng Wei (IEEE Trans. Computers, 2000)

Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers. - Milos D. Ercegovac; Tomás Lang; Jean-Michel Muller; Arnaud Tisserand (IEEE Trans. Computers, 2000)

FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization. - Zhijun Huang; Milos D. Ercegovac (FCCM, 2001)

A FPGA-based Library for On-Line Signal Processing. - Dannie Lau; Aaron Schneider; Milos D. Ercegovac; John D. Villasenor (J. VLSI Signal Process., 2001)

High-Radix Logarithm with Selection by Rounding. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (ASAP, 2002)

Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (ICCD, 2002)

Two-dimensional signal gating for low-power array multiplier design. - Zhijun Huang; Milos D. Ercegovac (ISCAS (1), 2002)

High-Level Synthesis with SIMD Units. - Vijay Raghunathan; Anand Raghunathan; Mani B. Srivastava; Milos D. Ercegovac (ASP-DAC/VLSI Design, 2002)

High-Performance Left-to-Right Array Multiplier Design. - Zhijun Huang; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 2003)

High-Radix Iterative Algorithm for Powering Computation. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (IEEE Symposium on Computer Arithmetic, 2003)

On-line high-radix exponential with selection by rounding. - José-Alejandro Piñeiro; Javier D. Bruguera; Milos D. Ercegovac (ISCAS (4), 2003)

Comments on "A carry-free 54 b×54 b multiplier using equivalent bit conversion algorithm". - Milos D. Ercegovac; Tomás Lang; Y. Kim; Bang-Sup Song; John Grosspietsch; Steven F. Gillig (IEEE J. Solid State Circuits, 2003)

Performance-driven mapping for CPLD architectures. - Deming Chen; Jason Cong; Milos D. Ercegovac; Zhijun Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

From the University of Illinois via JPL and UCLA to Vytautas Magnus University - 50 years of computer engineering by Algirdas Avizienis. - David A. Rennels; Milos D. Ercegovac (IFIP Congress Topical Sessions, 2004)

Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (IEEE Trans. Computers, 2004)

A Linear-System Operator Based Scheme for Evaluation of Multinomials. - Pavan Adharapurapu; Milos D. Ercegovac (IEEE Symposium on Computer Arithmetic, 2005)

Variable Radix Real and Complex Digit-Recurrence Division. - Milos D. Ercegovac; Jean-Michel Muller (ASAP, 2005)

RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions. - Robert McIlhenny; Milos D. Ercegovac (FCCM, 2005)

High-Performance Low-Power Left-to-Right Array Multiplier Design. - Zhijun Huang; Milos D. Ercegovac (IEEE Trans. Computers, 2005)

High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (J. VLSI Signal Process., 2005)

A Hardware-Oriented Method for Evaluating Complex Polynomials. - Milos D. Ercegovac; Jean-Michel Muller (ASAP, 2007)

A Design Method for Heterogeneous Adders. - Jeong-Gun Lee; Jeong-A Lee; Byeong-Seok Lee; Milos D. Ercegovac (ICESS, 2007)

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. - Thomas Y. Yeh; Petros Faloutsos; Milos D. Ercegovac; Sanjay J. Patel; Glenn Reinman (MICRO, 2007)

Complex Square Root with Operand Prescaling. - Milos D. Ercegovac; Jean-Michel Muller (J. VLSI Signal Process., 2007)

Design and FPGA implementation of radix-10 algorithm for division with limited precision primitives. - Milos D. Ercegovac; Robert McIlhenny (ACSCC, 2008)

An efficient method for evaluating polynomial and rational function approximations. - Nicolas Brisebarre; Sylvain Chevillard; Milos D. Ercegovac; Jean-Michel Muller; Serge Torres (ASAP, 2008)

Digital Arithmetic. - Florent de Dinechin; Milos D. Ercegovac; Jean-Michel Muller; Nathalie Revol (Wiley Encyclopedia of Computer Science and Engineering, 2008)

Design and Implementation of a Radix-4 Complex Division Unit with Prescaling. - Pouya Dormiani; Milos D. Ercegovac; Jean-Michel Muller (ASAP, 2009)

A radix-8 complex divider for FPGA implementation. - Dong Wang 040; Milos D. Ercegovac; Nanning Zheng 001 (FPL, 2009)

Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming. - Sanghoon Kwak; Jeong-Gun Lee; Eun-Gu Jung; Dongsoo Har; Milos D. Ercegovac; Jeong-A Lee (J. Circuits Syst. Comput., 2009)

Implementing decimal floating-point arithmetic through binary: Some suggestions. - Nicolas Brisebarre; Nicolas Louvet; Érik Martin-Dorel; Jean-Michel Muller; Adrien Panhaleux; Milos D. Ercegovac (ASAP, 2010)

Combining leak-resistant arithmetic for elliptic curves defined over Fp and RNS representation. - Jean-Claude Bajard; Sylvain Duquesne; Milos D. Ercegovac (IACR Cryptol. ePrint Arch., 2010)

Design of High-Throughput Fixed-Point Complex Reciprocal/Square-Root Unit. - Dong Wang 040; Milos D. Ercegovac; Nanning Zheng 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

An Efficient Method for Evaluating Complex Polynomials. - Milos D. Ercegovac; Jean-Michel Muller (J. Signal Process. Syst., 2010)

Shared implementation of radix-10 and radix-16 division algorithm with limited precision primitives. - Milos D. Ercegovac; Robert McIlhenny (ACSCC, 2011)

Accelerating the photon mapping algorithm and its hardware implementation. - Shawn Singh; Seung hyun Pan; Milos D. Ercegovac (ASAP, 2011)

Trading Accuracy for Power with an Underdesigned Multiplier Architecture. - Parag Kulkarni; Puneet Gupta 001; Milos D. Ercegovac (VLSI Design, 2011)

Trading Accuracy for Power in a Multiplier Architecture. - Parag Kulkarni; Puneet Gupta 001; Milos D. Ercegovac (J. Low Power Electron., 2011)

Linearization using efficient complex polynomial evaluations. - Pouya Dormiani; Milos D. Ercegovac (ACSCC, 2012)

Session TP8a3: Design methodology and computer arithmetic. - Milos D. Ercegovac (ACSCC, 2012)

Shared implementation of radix-10 and radix-16 square root algorithm with limited precision primitives. - Milos D. Ercegovac; Robert McIlhenny (ACSCC, 2012)

(M, p, k)-Friendly Points: A Table-Based Method for Trigonometric Function Evaluation. - Nicolas Brisebarre; Milos D. Ercegovac; Jean-Michel Muller (ASAP, 2012)

A Radix-16 Combined Complex Division/Square Root Unit with Operand Prescaling. - Dong Wang 040; Milos D. Ercegovac (IEEE Trans. Computers, 2012)

On approximate arithmetic. - Milos D. Ercegovac (ACSSC, 2013)

Power optimization of sum-of-products design for signal processing applications. - Seok Won Heo; Suk Joong Huh; Milos D. Ercegovac (ASAP, 2013)

Power optimization in a parallel multiplier using voltage islands. - Seok Won Heo; Suk Joong Huh; Milos D. Ercegovac (ISCAS, 2013)

Energy-efficient computing using adaptive table lookup based on nonvolatile memories. - Jason Cong; Milos D. Ercegovac; Muhuan Huang; Sen Li; Bingjun Xiao (ISLPED, 2013)

Low-power radix-4 quotient generator. - Milos D. Ercegovac; Lu Meng (ACSSC, 2014)

RF digital predistorter implementation using polynomial optimization. - Hojat Parta; Milos D. Ercegovac; Sudhakar Pamarti (MWSCAS, 2014)

Complex Function Approximation Using Two-Dimensional Interpolation. - Dong Wang 040; Milos D. Ercegovac; Yang Xiao 004 (IEEE Trans. Computers, 2014)

(M, p, k)-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function. - Dong Wang 040; Jean-Michel Muller; Nicolas Brisebarre; Milos D. Ercegovac (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An error-compensated piecewise linear logarithmic arithmetic unit for phong lighting acceleration. - Ching-En Lee; Milos D. Ercegovac (ACSSC, 2015)

Radix-4 energy efficient carry-free truncated multiplier. - Wen Yan; Milos D. Ercegovac (ACSSC, 2016)

An Energy-Efficient Multiplier With Fully Overlapped Partial Products Reduction and Final Addition. - Wen Yan; Milos D. Ercegovac; He Chen 004 (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

On left-to-right arithmetic. - Milos D. Ercegovac (ACSSC, 2017)

Conditional Estimation of Residuals with Prescaling for Use in Low-Energy Division Units. - Milos D. Ercegovac; James E. Stine (ACSSC, 2019)

On Reducing Module Activities in Online Arithmetic Operations. - Milos D. Ercegovac (ACSSC, 2020)

An Architecture for Improving Variable Radix Real and Complex Division Using Recurrence Division. - James E. Stine; Milos D. Ercegovac; Jean-Michel Muller (ACSSC, 2020)

Adder with Reduced Latency and Minimized Interconnect for Streaming Inner Products. - Tooba Arifeen; Abdus Sami Hassan; Jeong-A Lee; Milos D. Ercegovac (ACSCC, 2021)

Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. - Muhammad Usman; Jeong-A Lee; Milos D. Ercegovac (ACSCC, 2021)

An Efficient Dot-Product Unit Based on Online Arithmetic for Variable Precision Applications. - Saeid Gorgin 001; Mohammad H. Golamrezaei; Jeong-A Lee; Milos D. Ercegovac (ACSSC, 2023)

MSDF-SVM: Advantage of Most Significant Digit First Arithmetic for SVM Realization. - Saeid Gorgin 001; Mohammadreza Najafi; Mohammad H. Golamrezaei; Jeong-A Lee; Milos D. Ercegovac (ACSSC, 2023)

Multiplier Optimization via E-Graph Rewriting. - Andy Wanna; Samuel Coward; Theo Drane; George A. Constantinides; Milos D. Ercegovac (ACSSC, 2023)

Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product. - Tooba Arifeen; Saeid Gorgin 001; MohammadHosein Gholamrezaei; Abdus Sami Hassan; Milos D. Ercegovac; Jeong-A Lee (J. Signal Process. Syst., 2023)

Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. - Muhammad Usman; Milos D. Ercegovac; Jeong-A Lee (J. Signal Process. Syst., 2023)

Unified Digit Selection for Radix-4 Recurrence Division and Square Root. - David M. Harris; James E. Stine; Milos D. Ercegovac; Alberto Nannarelli; Katherine Parry; Cedar Turek (IEEE Trans. Computers, 2024)