Buffered Steiner trees for difficult instances. - Charles J. Alpert; Milos Hrkic; Jiang Hu; Andrew B. Kahng; John Lillis; Bao Liu 001; Stephen T. Quay; Sachin S. Sapatnekar; A. J. Sullivan; Paul Villarrubia (ISPD, 2001)

S-Tree: a technique for buffered routing tree synthesis. - Milos Hrkic; John Lillis (DAC, 2002)

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. - Milos Hrkic; John Lillis (ISPD, 2002)

Porosity aware buffered steiner tree construction. - Charles J. Alpert; Gopal Gandham; Milos Hrkic; Jiang Hu; Stephen T. Quay (ISPD, 2003)

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. - Milos Hrkic; John Lillis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Fast and flexible buffer trees that navigate the physical layout environment. - Charles J. Alpert; Milos Hrkic; Jiang Hu; Stephen T. Quay (DAC, 2004)

A fast algorithm for identifying good buffer insertion candidate locations. - Charles J. Alpert; Milos Hrkic; Stephen T. Quay (ISPD, 2004)

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. - Charles J. Alpert; Chris C. N. Chu; Gopal Gandham; Milos Hrkic; Jiang Hu; Chandramouli V. Kashyap; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Porosity-aware buffered Steiner tree construction. - Charles J. Alpert; Gopal Gandham; Milos Hrkic; Jiang Hu; Stephen T. Quay; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Techniques for improved placement-coupled logic replication. - Hosung (Leo) Kim; John Lillis; Milos Hrkic (ACM Great Lakes Symposium on VLSI, 2006)

An Approach to Placement-Coupled Logic Replication. - Milos Hrkic; John Lillis; Giancarlo Beraudo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Generalized Buffer Insertion. - Milos Hrkic; John Lillis (Handbook of Algorithms for Physical Design Automation, 2008)