A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (VLSI-SoC, 2005)

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (IJCNN, 2006)

Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. - Milos Stanisavljevic; Frank K. Gürkaynak; Alexandre Schmid; Yusuf Leblebici; Maria Gabrani (ACM Great Lakes Symposium on VLSI, 2007)

A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density. - Milos Stanisavljevic; Frank Kagan Gürkaynak; Alexandre Schmid; Yusuf Leblebici; Maria Gabrani (Nano-Net, 2007)

An Enhanced Service Provider Communication Interface with Client Prioritization - Case Study on Fast-food Chain Restaurants. - Slobodan Lukovic; Nikola Puzovic; Milos Stanisavljevic (ICE-B, 2008)

Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR). - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (DFT, 2009)

Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (NanoNet, 2009)

On the Reliability of Post-CMOS and SET Systems. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (Int. J. Nanotechnol. Mol. Comput., 2009)

Selective redundancy-based design techniques for the minimization of local delay variations. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (ISCAS, 2010)

Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (VLSI-SoC, 2010)

A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory. - Aravinthan Athmanathan; Milos Stanisavljevic; Junho Cheon; Seokjoon Kang; Changyong Ahn; Junghyuk Yoon; Min-Chul Shin; Taekseung Kim; Nikolaos Papandreou; Haris Pozidis; Evangelos Eleftheriou (A-SSCC, 2014)

Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology. - Junho Cheon; Insoo Lee; Changyong Ahn; Milos Stanisavljevic; Aravinthan Athmanathan; Nikolaos Papandreou; Haris Pozidis; Evangelos Eleftheriou; Min-Chul Shin; Taekseung Kim; Jong-Ho Kang; Jun Hyun Chun (CICC, 2015)

Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures. - Milos Stanisavljevic; Aravinthan Athmanathan; Nikolaos Papandreou; Haralampos Pozidis; Evangelos Eleftheriou (IRPS, 2015)

Multilevel-Cell Phase-Change Memory: A Viable Technology. - Aravinthan Athmanathan; Milos Stanisavljevic; Nikolaos Papandreou; Haralampos Pozidis; Evangelos Eleftheriou (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

A Fast and Scalable Pipeline for Stain Normalization of Whole-Slide Images in Histopathology. - Milos Stanisavljevic; Andreea Anghel; Nikolaos Papandreou; Sonali Andani; Pushpak Pati; Jan Hendrik Rüschoff; Peter Wild; Maria Gabrani; Haralampos Pozidis (ECCV Workshops (6), 2018)

Drift-Invariant Detection for Multilevel Phase-Change Memory. - Milos Stanisavljevic; Thomas Mittelholzer; Nikolaos Papandreou; Thomas P. Parnell; Haralampos Pozidis (ISCAS, 2018)

Accelerated ML-Assisted Tumor Detection in High-Resolution Histopathology Images. - Nikolas Ioannou; Milos Stanisavljevic; Andreea Anghel; Nikolaos Papandreou; Sonali Andani; Jan Hendrik Rüschoff; Peter Wild; Maria Gabrani; Haralampos Pozidis (MICCAI (1), 2019)

Reliability of 3D NAND flash memory with a focus on read voltage calibration from a system aspect. - Nikolaos Papandreou; Nikolas Ioannou; Thomas P. Parnell; Roman A. Pletka; Milos Stanisavljevic; Radu Stoica; Sasa Tomic; Haralampos Pozidis (NVMTS, 2019)

Deep learning acceleration based on in-memory computing. - Evangelos Eleftheriou; Manuel Le Gallo; S. R. Nandakumar; Christophe Piveteau; Irem Boybat; Vinay Joshi; Riduan Khaddam-Aljameh; Martino Dazzi; Iason Giannopoulos; Geethan Karunaratne; Benedikt Kersting; Milos Stanisavljevic; et al. (IBM J. Res. Dev., 2019)

Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash. - Nikolaos Papandreou; Haralampos Pozidis; Nikolas Ioannou; Thomas P. Parnell; Roman A. Pletka; Milos Stanisavljevic; Radu Stoica; Sasa Tomic; Patrick Breen; Gary A. Tressler; Aaron Fry; Timothy Fisher; et al. (IRPS, 2020)

High-Throughput ECC with Integrated Chipkill Protection for Nonvolatile Memory Arrays. - Thomas Mittelholzer; Milos Stanisavljevic; Nikolaos Papandreou; Haralampos Pozidis (ISCAS, 2021)

HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing. - Riduan Khaddam-Aljameh; Milos Stanisavljevic; Jordi Fornt Mas; Geethan Karunaratne; Matthias Braendli; Femg Liu; Abhairaj Singh; Silvia M. Müller; Urs Egger; Anastasios Petropoulos; Theodore Antonakopoulos 001; Kevin Brew; et al. (VLSI Circuits, 2021)

Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices. - Katie Spoon; Hsinyu Tsai; An Chen 002; Malte J. Rasch; Stefano Ambrogio; Charles Mackin; Andrea Fasoli; Alexander M. Friz; Pritish Narayanan; Milos Stanisavljevic; Geoffrey W. Burr (Frontiers Comput. Neurosci., 2021)

Circuit and System-Level Aspects of Phase Change Memory. - Haralampos Pozidis; Nikolaos Papandreou; Milos Stanisavljevic (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. - Manuel Le Gallo; Riduan Khaddam-Aljameh; Milos Stanisavljevic; Athanasios Vasilopoulos; Benedikt Kersting; Martino Dazzi; Geethan Karunaratne; Matthias Braendli; Abhairaj Singh; Silvia M. Mueller; Julian Büchel; Xavier Timoneda Comas; et al. (CoRR, 2022)

HERMES-Core - A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs. - Riduan Khaddam-Aljameh; Milos Stanisavljevic; Jordi Fornt Mas; Geethan Karunaratne; Matthias Brändli; Feng Liu; Abhairaj Singh; Silvia M. Müller; Urs Egger; Anastasios Petropoulos; Theodore Antonakopoulos 001; Kevin Brew; et al. (IEEE J. Solid State Circuits, 2022)

Acceleration of Decision-Tree Ensemble Models on the IBM Telum Processor. - Nikolaos Papandreou; Jan van Lunteren; Andreea Anghel; Thomas P. Parnell; Martin Petermann; Milos Stanisavljevic; Cédric Lichtenau; Andrew Sica; Dominic Röhm; Elpida Tzortzatos; Haralampos Pozidis (ISCAS, 2023)

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh. - Shubham Jain; Hsinyu Tsai; Ching-Tzu Chen; Ramachandran Muralidhar; Irem Boybat; Martin M. Frank; Stanislaw Wozniak; Milos Stanisavljevic; Praneet Adusumilli; Pritish Narayanan; Kohji Hosokawa; Masatoshi Ishii; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2023)

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge. - Pascal Alexander Hager; Bert Moons; Stefan Cosemans; Ioannis A. Papistas; Bram Rooseleer; Jeroen Van Loon; Roel Uytterhoeven; Florian Zaruba; Spyridoula Koumousi; Milos Stanisavljevic; Stefan Mach; Sebastiaan Mutsaards; et al. (ISSCC, 2024)