Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design. - Min Chen 024; Yu Cao 001 (ISQED, 2006)

Fast statistical circuit analysis with finite-point based transistor model. - Min Chen 024; Wei Zhao; Frank Liu 001; Yu Cao 001 (DATE, 2007)

Variability analysis under layout pattern-dependent rapid-thermal annealing process. - Yun Ye; Frank Liu 001; Min Chen 024; Yu Cao 001 (DAC, 2009)

Modeling of layout-dependent stress effect in CMOS design. - Chi-Chao Wang; Wei Zhao; Frank Liu 001; Min Chen 024; Yu Cao 001 (ICCAD, 2009)

Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation. - Min Chen 024; Wei Zhao; Frank Liu 001; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

In-situ characterization and extraction of SRAM variability. - Srivatsan Chellappa; Jia Ni; Xiaoyin Yao; Nathan D. Hindman; Jyothi Velamala; Min Chen 024; Yu Cao 001; Lawrence T. Clark (DAC, 2010)

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness. - Yun Ye; Frank Liu 001; Min Chen 024; Sani R. Nassif; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors. - Min Chen 024; Vijay Reddy; Srikanth Krishnan; Venkatesh Srinivasan; Yu Cao 001 (IEEE Des. Test Comput., 2012)

ACE: A robust variability and aging sensor for high-k/metal gate SoC. - Min Chen 024; Vijay Reddy; Srikanth Krishnan; Jay Ondrusek; Yu Cao 001 (ESSDERC, 2013)

Reliability improvement of logic and clock paths in power-efficient designs. - Senthil Arasu; Mehrdad Nourani; Vijay Reddy; John M. Carulli Jr.; Gautam Kapila; Min Chen 024 (ACM J. Emerg. Technol. Comput. Syst., 2014)

Recovery modeling of negative bias temperature instability (NBTI) for SPICE-compatible circuit aging simulators. - Haldun Küflüoglu; Cathy Chancellor; Min Chen 024; Claude Cirba; Vijay Reddy (ACM J. Emerg. Technol. Comput. Syst., 2014)