A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS. - Dong-Ryeol Oh; Jong-In Kim; Min-Jae Seo; Jin-Gwang Kim; Seung-Tak Ryu (ESSCIRC, 2015)

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. - Wan Kim; Hyeok-Ki Hong; Yi-Ju Roh; Hyun-Wook Kang; Sun-Il Hwang; Dong-Shin Jo; Dong-Jin Chang; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2016)

Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC. - Dong-Jin Chang; Wan Kim; Min-Jae Seo; Hyeok-Ki Hong; Seung-Tak Ryu (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. - Il-Hoon Jang; Min-Jae Seo; Sang-Hyun Cho; Jae-Keun Lee; Seung-Yeob Baek 002; Sunwoo Kwon; Michael Choi; Hyungjong Ko; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration. - Dong-Jin Chang; Min-Jae Seo; Hyeok-Ki Hong; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs. - Si-Nai Kim; Woo-Cheol Kim; Min-Jae Seo; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Sun-Il Hwang; Jong-Pal Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. - Min-Jae Seo; Yi-Ju Roh; Dong-Jin Chang; Wan Kim; Ye-Dam Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Jong-Pal Kim; Dong-Jin Chang; Won-Mook Lim; Jae-Hyun Chung; Chang-Un Park; Eun-Ji An; Seung-Tak Ryu (A-SSCC, 2019)

A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. - Min-Jae Seo; Ye-Dam Kim; Jae-Hyun Chung; Seung-Tak Ryu (VLSI Circuits, 2019)

A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers. - Dong-Hwan Jin; Ji-Wook Kwon; Min-Jae Seo; Mi-Young Kim; Min-Chul Shin; Seokjoon Kang; Junghyuk Yoon; Taek-Seung Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2019)

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section. - Jongpal Kim; Wonseok Lee; Junyeub Suh; Hyungwoo Lee; Kyu-Il Lee; Ho Young Ahn; Min-Jae Seo; Seung-Tak Ryu; Kirill Y. Aristovich; David S. Holder; Sang Joon Kim (EMBC, 2020)

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Jong-Pal Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2020)

A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration. - Dong-Shin Jo; Ba-Ro-Saim Sung; Min-Jae Seo; Woo-Cheol Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique. - Dong-Ryeol Oh; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2022)

An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. - Jae-Hyun Chung; Ye-Dam Kim; Chang-Un Park; Kun-Woo Park; Min-Jae Seo; Seung-Tak Ryu (CICC, 2023)

A Hardware-efficient Rate Encoding Hardware with Latch-based TRNG. - Sun-A Jo; Ji-Won Seo; Min-Jae Seo (ICEIC, 2024)

A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF. - Ye-Dam Kim; Jae-Hyun Chung; Kent Edrian Lozada; Chang-Un Park; Kun-Woo Park; Kwan-Hoon Song; Young-Hun Moon; Min-Jae Seo; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. - Jae-Hyun Chung; Ye-Dam Kim; Chang-Un Park; Kun-Woo Park; Dong-Ryeol Oh; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2024)

An M-Metric Readout Circuit for MLC Phase-Change Memory With a Comparator-Based Push-Pull Bit-Line Driver. - Ji-Wook Kwon; Dong-Hwan Jin; Min-Jae Seo; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)