A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS. - Sergey Romanovsky; Atul Katoch; Arun Achyuthan; C. O'Connell; Sreedhar Natarajan; C. Huang; Chuan-Yu Wu; Min-Jer Wang; C. J. Wang; P. Chen; R. Hsieh (ISSCC, 2008)

A memory yield improvement scheme combining built-in self-repair and error correction codes. - Tze-Hsin Wu; Po-Yuan Chen; Mincent Lee; Bin-Yen Lin; Cheng-Wen Wu; Chen-Hung Tien; Hung-Chih Lin; Hao Chen 053; Ching-Nen Peng; Min-Jer Wang (ITC, 2012)

A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS. - Peter Kuoyuan Hsu; Yukit Tang; Derek Tao; Ming-Chieh Huang; Min-Jer Wang; C. H. Wu; Quincy Lee (VLSIC, 2012)

A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB. - Ming-Zhang Kuo; Osamu Takahashi; Ping-Lin Yang; Cheng-Chung Lin; Min-Jer Wang; Ping-Wei Wang; Sang H. Dhong (CICC, 2013)

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. - Sandeep Kumar Goel; Saman Adham; Min-Jer Wang; Ji-Jan Chen; Tze-Chiang Huang; Ashok Mehta; Frank Lee 004; Vivek Chickermane; Brion L. Keller; Thomas Valind; Subhasish Mukherjee; Navdeep Sood; et al. (ITC, 2013)

Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch. - Sen-Kuei Hsu; Hao Chen 053; Chung-Han Huang; Der-Jiann Liu; Wei-Hsun Lin; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2013)

3D-IC interconnect test, diagnosis, and repair. - Chun-Chuan Chi; Cheng-Wen Wu; Min-Jer Wang; Hung-Chih Lin (VTS, 2013)

A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. - Sang H. Dhong; Richard Guo; Ming-Zhang Kuo; Ping-Lin Yang; Cheng-Chung Lin; Kevin Huang 005; Min-Jer Wang; Wei Hwang (CICC, 2014)

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. - Ming-Zhang Kuo; Henry Hsieh; Sang H. Dhong; Ping-Lin Yang; Cheng-Chung Lin; Ryan Tseng; Kevin Huang 005; Min-Jer Wang; Wei Hwang (CICC, 2014)

Wafer Level Chip Scale Package copper pillar probing. - Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2014)

Redundancy architectures for channel-based 3D DRAM yield improvement. - Bing-Yang Lin; Wan-Ting Chiang; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2014)

Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs. - Sandeep Kumar Goel; Min-Jer Wang; Saman Adham; Ashok Mehta; Frank Lee 004 (VLSI-DAT, 2014)

A novel DFT architecture for 3DIC test, diagnosis and repair. - Mincent Lee; Saman Adham; Min-Jer Wang; Ching-Nen Peng; Hung-Chih Lin; Sen-Kuei Hsu; Hao Chen 053 (VLSI-DAT, 2014)

A 4-GHz universal high-frequency on-chip testing platform for IP validation. - Ping-Lin Yang; Cheng-Chung Lin; Ming-Zhang Kuo; Sang-Hoo Dhong; Chien-Min Lin; Kevin Huang 005; Ching-Nen Peng; Min-Jer Wang (VTS, 2014)

On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. - Chun-Chuan Chi; Bing-Yang Lin; Cheng-Wen Wu; Min-Jer Wang; Hung-Chih Lin; Ching-Nen Peng (IEEE Des. Test, 2014)

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. - Mu-Shan Lin; Chien-Chun Tsai; Chih-Hsien Chang; Wen-Hung Huang; Ying-Yu Hsu; Shu-Chun Yang; Chin-Ming Fu; Mao-Hsuan Chou; Tien-Chien Huang; Ching-Fang Chen; Tze-Chiang Huang; Saman Adham; et al. (IEEE J. Solid State Circuits, 2014)

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. - Henry Hsieh; Sang H. Dhong; Cheng-Chung Lin; Ming-Zhang Kuo; Kuo-Feng Tseng; Ping-Lin Yang; Kevin Huang 005; Min-Jer Wang; Wei Hwang (CICC, 2015)

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. - Yu-Chieh Huang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (DAC, 2016)

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. - Bing-Yang Lin; Wan-Ting Chiang; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Des. Test, 2016)

A Local Parallel Search Approach for Memory Failure Pattern Identification. - Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Trans. Computers, 2016)

Fan-out wafer level chip scale package testing. - Hao Chen 053; Hung-Chih Lin; Min-Jer Wang (ITC-Asia, 2017)

Testing-for-manufacturing (TFM) for ultra-thin IPD on InFO. - Tang-Jung Chiu; Yu-Lun Tseng; Yen-Cheng Lin; Yi-Chen Wang; Hung-Chih Lin; Min-Jer Wang (ITC-Asia, 2017)

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. - Kai-Li Wang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Des. Test, 2017)

A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. - Hsuan-Hung Liu; Bing-Yang Lin; Cheng-Wen Wu; Wan-Ting Chiang; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Trans. Computers, 2017)

High Quality Test Methodology for Highly Reliable Devices. - Hao Chen 053; Mincent Lee; Liang-Yen Chen; Min-Jer Wang (ITC, 2019)

Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill. - Mincent Lee; Cheng-Tse Lu; Chia-Heng Tsai; Hao Chen 053; Min-Jer Wang (ITC-Asia, 2020)

Novel Circuit Probing for Tiny Inductor. - Chia-Heng Tsai; Chi-Chang Lai; Hao Chen 053; Min-Jer Wang (ITC-Asia, 2020)

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. - Chien-Hui Chuang; Kuan-Wei Hou; Cheng-Wen Wu; Mincent Lee; Chia-Heng Tsai; Hao Chen 053; Min-Jer Wang (ITC, 2020)