D2NN: a fine-grained dual modular redundancy framework for deep neural networks. - Yu Li 007; Yannan Liu; Min Li 019; Ye Tian 010; Bo Luo; Qiang Xu 001 (ACSAC, 2019)

Lightweight prediction based big/little design for efficient neural network inference. - Ye Tian 010; Min Li 019; Qiang Xu 001 (SEC, 2019)

DeepDyve: Dynamic Verification for Deep Neural Networks. - Yu Li 007; Min Li 019; Bo Luo; Ye Tian 010; Qiang Xu 001 (CCS, 2020)

On Configurable Defense against Adversarial Example Attacks. - Bo Luo; Min Li 019; Yu Li 007; Qiang Xu 001 (ACM Great Lakes Symposium on VLSI, 2020)

Skimming and Scanning for Efficient Action Recognition in Untrimmed Videos. - Yunyan Hong; Ailing Zeng; Min Li 019; Cewu Lu; Li Jiang 002; Qiang Xu 001 (CISP-BMEI, 2021)

AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference. - Min Li 019; Yu Li 007; Ye Tian 010; Li Jiang 002; Qiang Xu 001 (DAC, 2021)

Testability-Aware Low Power Controller Design with Evolutionary Learning. - Min Li 019; Zhengyuan Shi; Zezhong Wang 006; Weiwei Zhang; Yu Huang 005; Qiang Xu 001 (ITC, 2021)

TestRank: Bringing Order into Unlabeled Test Instances for Deep Learning Tasks. - Yu Li 007; Min Li 019; Qiuxia Lai; Yannan Liu; Qiang Xu 001 (NeurIPS, 2021)

Skimming and Scanning for Untrimmed Video Action Recognition. - Yunyan Hong; Ailing Zeng; Min Li 019; Cewu Lu; Li Jiang 002; Qiang Xu 001 (CoRR, 2021)

Representation Learning of Logic Circuits. - Min Li 019; Sadaf Khan; Zhengyuan Shi; Naixing Wang; Yu Huang 005; Qiang Xu 001 (CoRR, 2021)

DeepGate: learning neural representations of logic gates. - Min Li 019; Sadaf Khan; Zhengyuan Shi; Naixing Wang; Huang Yu; Qiang Xu 001 (DAC, 2022)

T-WaveNet: A Tree-Structured Wavelet Neural Network for Time Series Signal Analysis. - Minhao Liu; Ailing Zeng; Qiuxia Lai; Ruiyuan Gao 001; Min Li 019; Jing Qin 001; Qiang Xu 001 (ICLR, 2022)

DeepTPI: Test Point Insertion with Deep Reinforcement Learning. - Zhengyuan Shi; Min Li 019; Sadaf Khan; Liuzheng Wang; Naixing Wang; Yu Huang 005; Qiang Xu 001 (ITC, 2022)

DeepSAT: An EDA-Driven Learning Framework for SAT. - Min Li 019; Zhengyuan Shi; Qiuxia Lai; Sadaf Khan; Qiang Xu 001 (CoRR, 2022)

SATformer: Transformers for SAT Solving. - Zhengyuan Shi; Min Li 019; Sadaf Khan; Hui-Ling Zhen; Mingxuan Yuan; Qiang Xu 001 (CoRR, 2022)

On EDA-Driven Learning for SAT Solving. - Min Li 019; Zhengyuan Shi; Qiuxia Lai; Sadaf Khan; Shaowei Cai 001; Qiang Xu 001 (DAC, 2023)

SATformer: Transformer-Based UNSAT Core Learning. - Zhengyuan Shi; Min Li 019; Yi Liu; Sadaf Khan; Junhua Huang; Hui-Ling Zhen; Mingxuan Yuan; Qiang Xu 001 (ICCAD, 2023)

DeepGate2: Functionality-Aware Circuit Representation Learning. - Zhengyuan Shi; Hongyang Pan; Sadaf Khan; Min Li 019; Yi Liu; Junhua Huang; Hui-Ling Zhen; Mingxuan Yuan; Zhufei Chu; Qiang Xu 001 (ICCAD, 2023)

Addressing Variable Dependency in GNN-based SAT Solving. - Zhiyuan Yan 003; Min Li 019; Zhengyuan Shi; Wenjie Zhang; Yingcong Chen; Hongce Zhang (CoRR, 2023)

DeepSeq: Deep Sequential Circuit Learning. - Sadaf Khan; Zhengyuan Shi; Min Li 019; Qiang Xu 001 (DATE, 2024)

AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model Prediction. - Zhiyuan Yan 003; Min Li 019; Zhengyuan Shi; Wenjie Zhang; Yingcong Chen; Hongce Zhang (DATE, 2024)

DeepGate3: Towards Scalable Circuit Representation Learning. - Zhengyuan Shi; Ziyang Zheng; Sadaf Khan; Jianyuan Zhong; Min Li 019; Qiang Xu 001 (ICCAD, 2024)

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. - Wenji Fang; Mengming Li; Min Li 019; Zhiyuan Yan 003; Shang Liu 006; Hongce Zhang; Zhiyao Xie (CoRR, 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

VerilogReader: LLM-Aided Hardware Test Generation. - Ruiyang Ma; Yuxin Yang; Ziqian Liu; Jiaxi Zhang 001; Min Li 019; Junhua Huang; Guojie Luo (CoRR, 2024)

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. - Zhiyuan Yan 003; Wenji Fang; Mengming Li; Min Li 019; Shang Liu 006; Zhiyao Xie; Hongce Zhang (ASP-DAC, 2025)

DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations. - Sadaf Khan; Zhengyuan Shi; Ziyang Zheng; Min Li 019; Qiang Xu 001 (ASP-DAC, 2025)