Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC. - Tongsheng Geng; Leibo Liu; Shouyi Yin; Min Zhu 001; Wen Jia; Shaojun Wei (ISCAS, 2010)

A reconfigurable multi-processor SoC for media applications. - Min Zhu 001; Leibo Liu; Shouyi Yin; Yansheng Wang; Wenjie Wang; Shaojun Wei (ISCAS, 2010)

Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System. - Tongsheng Geng; Leibo Liu; Shouyi Yin; Min Zhu 001; Shaojun Wei (IEICE Trans. Inf. Syst., 2010)

A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System. - Min Zhu 001; Leibo Liu; Shouyi Yin; Chongyong Yin; Shaojun Wei (IEICE Trans. Inf. Syst., 2010)

Reducing configuration contexts for coarse-grained reconfigurable architecture. - Shouyi Yin; Chongyong Yin; Leibo Liu; Min Zhu 001; Yansheng Wang; Shaojun Wei (ISCAS, 2012)

Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. - Bo Liu 019; Peng Cao 002; Min Zhu 001; Jun Yang 006; Leibo Liu; Shaojun Wei; Longxing Shi (IEICE Trans. Inf. Syst., 2012)

Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. - Xinning Liu; Chen Mei; Peng Cao 002; Min Zhu 001; Longxing Shi (IEICE Trans. Inf. Syst., 2012)

Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture. - Jian Xiao; Jinguo Zhang; Min Zhu 001; Jun Yang 006; Longxing Shi (IEICE Trans. Inf. Syst., 2012)

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture. - Shouyi Yin; Chongyong Yin; Leibo Liu; Min Zhu 001; Shaojun Wei (IEICE Trans. Inf. Syst., 2012)

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. - Leibo Liu; Chenchen Deng; Dong Wang 040; Min Zhu 001; Shouyi Yin; Peng Cao 002; Shaojun Wei (CICC, 2013)

Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (Sci. China Inf. Sci., 2013)

Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip. - Hung K. Nguyen; Peng Cao 002; Xuexiang Wang; Jun Yang 006; Longxing Shi; Min Zhu 001; Leibo Liu; Shaojun Wei (IEICE Trans. Inf. Syst., 2013)

The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture. - Leibo Liu; Yansheng Wang; Shouyi Yin; Min Zhu 001; Xing Wang; Shaojun Wei (Sci. China Inf. Sci., 2014)

SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration. - Leibo Liu; Dong Wang 040; Shouyi Yin; Yingjie Victor Chen; Min Zhu 001; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2014)

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only). - Leibo Liu; Yingjie Victor Chen; Dong Wang 040; Min Zhu 001; Shouyi Yin; Shaojun Wei (FPGA, 2015)

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform. - Leibo Liu; Dong Wang 040; Yingjie Chen; Min Zhu 001; Shouyi Yin; Shaojun Wei (IEICE Trans. Inf. Syst., 2016)

Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture. - Bo Wang 023; Leibo Liu; Chenchen Deng; Min Zhu 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Inf. Forensics Secur., 2016)

Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks. - Bo Wang 023; Leibo Liu; Chenchen Deng; Min Zhu 001; Shouyi Yin; Zhuoquan Zhou; Shaojun Wei (IEEE Trans. Inf. Forensics Secur., 2017)

A Deep Learning Modeling Attack Method for MISR-APUF Protection Structures. - Wei Ge; Ji Quan Huang; Bo Liu 019; Min Zhu 001; Yuan Cao 003 (APCCAS, 2018)

A Fully Digital Physical Unclonable Function Based Temperature Sensor for Secure Remote Sensing. - Yuan Cao 003; Yunyi Guo; Benyu Liu; Wei Ge; Min Zhu 001; Chip-Hong Chang (ICCCN, 2018)

Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms. - Leibo Liu; Bo Wang 023; Chenchen Deng; Min Zhu 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures. - Leibo Liu; Zhuoquan Zhou; Shaojun Wei; Min Zhu 001; Shouyi Yin; Shengyang Mao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Umbrella: Enabling ISPs to Offer Readily Deployable and Privacy-Preserving DDoS Prevention Services. - Zhuotao Liu; Yuan Cao 003; Min Zhu 001; Wei Ge (IEEE Trans. Inf. Forensics Secur., 2019)

A High-throughput Low-area Entropy Source Based on Asynchronous Feedback Unit. - Ping Wang; Jinjiang Yang; Min Zhu 001; Bo Liu 019 (ICCSP, 2020)

Dynamic feedback stabilization of an unstable wave equation. - Yu-Long Zhang; Min Zhu 001; Donghai Li; Jun-Min Wang (Autom., 2020)

A High-performance Hardware Implementation of Saber Based on Karatsuba Algorithm. - Yihong Zhu; Min Zhu 001; Bohan Yang 001; Wenping Zhu; Chenchen Deng; Chen Chen 083; Shaojun Wei; Leibo Liu (IACR Cryptol. ePrint Arch., 2020)

FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance. - Wei Ge; Shenxin Hu; Ji Quan Huang; Bo Liu 019; Min Zhu 001 (IEICE Electron. Express, 2020)

A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA. - Wei Ge; Shenghua Chen; Benyu Liu; Min Zhu 001; Bo Liu 019 (IEICE Trans. Inf. Syst., 2020)

ADRC Dynamic Stabilization of an Unstable Heat Equation. - Yu-Long Zhang; Min Zhu 001; Donghai Li; Jun-Min Wang (IEEE Trans. Autom. Control., 2020)

A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power. - Chenchen Deng; Bo Wang 023; Leibo Liu; Min Zhu 001; Youyu Wu; Hui Li; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Fast substitution-box evaluation algorithm and its efficient masking scheme for block ciphers. - Hai Huang; Leibo Liu; Min Zhu 001; Shouyi Yin; Shaojun Wei (Sci. China Inf. Sci., 2021)

Static boundary feedback stabilization of an anti-stable wave equation with both collocated and non-collocated measurements. - Yu-Long Zhang; Min Zhu 001; Donghai Li; Jun-Min Wang (Syst. Control. Lett., 2021)

LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR. - Yihong Zhu; Min Zhu 001; Bohan Yang 001; Wenping Zhu; Chenchen Deng; Chen Chen 083; Shaojun Wei; Leibo Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems. - Yihong Zhu; Wenping Zhu; Min Zhu 001; Chongyang Li; Chenchen Deng; Chen Chen 083; Shuying Yin; Shouyi Yin; Shaojun Wei; Leibo Liu (ISSCC, 2022)

Stabilization of two coupled wave equations with joint anti-damping and non-collocated control. - Yu-Long Zhang; Min Zhu 001; Donghai Li; Jun-Min Wang (Autom., 2022)

An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance. - Chenchen Deng; Min Zhu 001; Jinjiang Yang; Youyu Wu; Jiaji He; Bohan Yang 001; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (Sci. China Inf. Sci., 2022)

Compact GF(2) systemizer and optimized constant-time hardware sorters for Key Generation in Classic McEliece. - Yihong Zhu; Wenping Zhu; Chen Chen 083; Min Zhu 001; Zhengdong Li; Shaojun Wei; Leibo Liu (IACR Cryptol. ePrint Arch., 2022)

Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding. - Zongsheng Hou; Neng Zhang 002; Bohan Yang 001; Hanning Wang; Min Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium. - Cankun Zhao; Neng Zhang 002; Hanning Wang; Bohan Yang 001; Wenping Zhu; Zhengdong Li; Min Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware. - Yihong Zhu; Wenping Zhu; Chen Chen 083; Min Zhu 001; Zhengdong Li; Shaojun Wei; Leibo Liu (DAC, 2023)

RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems. - Yihong Zhu; Wenping Zhu; Chongyang Li; Min Zhu 001; Chenchen Deng; Chen Chen 083; Shuying Yin; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE J. Solid State Circuits, 2023)

A Closer Look at the Chaotic Ring Oscillators based TRNG Design. - Shuqin Su; Bohan Yang 001; Vladimir Rozic; Mingyuan Yang; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023)

16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems. - Yihong Zhu; Wenping Zhu; Yi Ouyang; Junwen Sun; Min Zhu 001; Qi Zhao; Jinjiang Yang; Chen Chen 083; Qichao Tao; Guang Yang; Aoyang Zhang; Shaojun Wei; et al. (ISSCC, 2024)

UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication. - Xiangren Chen; Bohan Yang 001; Jianfeng Zhu 001; Jun Liu; Shuying Yin; Guang Yang; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

A Low-Latency High-Order Arithmetic to Boolean Masking Conversion. - Jiangxue Liu; Cankun Zhao; Shuohang Peng; Bohan Yang 001; Hang Zhao; Xiangdong Han; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

Breaking Ground: A New Area Record for Low-Latency First-Order Masked SHA-3 Advancing from the 4x Area Era to the 3x Area Era. - Cankun Zhao; Hang Zhao; Jiangxue Liu; Bohan Yang 001; Wenping Zhu; Shuying Yin; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

17.2 A 28nm 4.05µJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing. - Sijia Lu; Wenping Zhu; Bohan Yang 001; Jiajun Yang; Tongwei Dai; Chen Chen 083; Xiangdong Han; Jinjiang Yang; Hanning Wang; Min Zhu 001; Shaojun Wei; Aoyang Zhang; et al. (ISSCC, 2025)

A High-performance NTT/MSM Accelerator for Zero-knowledge Proof Using Load-balanced Fully-pipelined Montgomery Multiplier. - Xiangren Chen; Bohan Yang 001; Wenping Zhu; Hanning Wang; Qichao Tao; Shuying Yin; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

On the Characterization of Phase Noise for the Robust and Resilient PLL-TRNG Design. - Ziheng Ma; Bohan Yang 001; Wenping Zhu; Hanning Wang; Yi Ouyang; Min Zhu 001; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

FalconSign: An Efficient and High-Throughput Hardware Architecture for Falcon Signature Generation. - Yi Ouyang; Yihong Zhu; Wenping Zhu; Bohan Yang 001; Zirui Zhang; Hanning Wang; Qichao Tao; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

Boundary PI Feedback Stabilization of Combustion Oscillations in the Rijke Tube. - Yu-Long Zhang; Shaojie Liu; Zhaohui Wang; Jun-Min Wang; Donghai Li; Min Zhu 001 (IEEE Trans. Autom. Control., 2025)

PQPU: A 4.4-μJ/Op 69.4-kOPS Agile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems. - Yihong Zhu; Wenping Zhu; Yi Ouyang; Junwen Sun; Qi Zhao; Min Zhu 001; Jinjiang Yang; Chen Chen 083; Qichao Tao; Hanning Wang; Guang Yang; Shaojun Wei; et al. (IEEE J. Solid State Circuits, 2025)