A Memory Built-In Self-Repair Scheme Based on Configurable Spares. - Mincent Lee; Li-Ming Denq; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A memory yield improvement scheme combining built-in self-repair and error correction codes. - Tze-Hsin Wu; Po-Yuan Chen; Mincent Lee; Bin-Yen Lin; Cheng-Wen Wu; Chen-Hung Tien; Hung-Chih Lin; Hao Chen 053; Ching-Nen Peng; Min-Jer Wang (ITC, 2012)

Cost modeling and analysis for interposer-based three-dimensional IC. - Ying-Wen Chou; Po-Yuan Chen; Mincent Lee; Cheng-Wen Wu (VTS, 2012)

A Memory Failure Pattern Analyzer for memory diagnosis and repair. - Bing-Yang Lin; Mincent Lee; Cheng-Wen Wu (VTS, 2012)

Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. - Bing-Yang Lin; Mincent Lee; Cheng-Wen Wu (Asian Test Symposium, 2013)

Redundancy architectures for channel-based 3D DRAM yield improvement. - Bing-Yang Lin; Wan-Ting Chiang; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2014)

A novel DFT architecture for 3DIC test, diagnosis and repair. - Mincent Lee; Saman Adham; Min-Jer Wang; Ching-Nen Peng; Hung-Chih Lin; Sen-Kuei Hsu; Hao Chen 053 (VLSI-DAT, 2014)

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. - Yu-Chieh Huang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (DAC, 2016)

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. - Bing-Yang Lin; Wan-Ting Chiang; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Des. Test, 2016)

A Local Parallel Search Approach for Memory Failure Pattern Identification. - Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Trans. Computers, 2016)

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. - Kai-Li Wang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Des. Test, 2017)

A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. - Hsuan-Hung Liu; Bing-Yang Lin; Cheng-Wen Wu; Wan-Ting Chiang; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Trans. Computers, 2017)

High Quality Test Methodology for Highly Reliable Devices. - Hao Chen 053; Mincent Lee; Liang-Yen Chen; Min-Jer Wang (ITC, 2019)

Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill. - Mincent Lee; Cheng-Tse Lu; Chia-Heng Tsai; Hao Chen 053; Min-Jer Wang (ITC-Asia, 2020)

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. - Chien-Hui Chuang; Kuan-Wei Hou; Cheng-Wen Wu; Mincent Lee; Chia-Heng Tsai; Hao Chen 053; Min-Jer Wang (ITC, 2020)

A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. - Pai-Yu Tan; Chih-Hsuan Tung; Cheng-Wen Wu; Mincent Lee; Gordon Liao (VLSI-DAT, 2022)