A gate leakage reduction strategy for future CMOS circuits. - Mindaugas Drazdziulis; Per Larsson-Edefors (ESSCIRC, 2003)

Evaluation of power cut-off techniques in the presence of gate leakage. - Mindaugas Drazdziulis; Per Larsson-Edefors (ISCAS (2), 2004)

A low-leakage twin-precision multiplier using reconfigurable power gating. - Magnus Själander; Mindaugas Drazdziulis; Per Larsson-Edefors; Henrik Eriksson (ISCAS (2), 2005)

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. - Minh Quang Do; Mindaugas Drazdziulis; Per Larsson-Edefors; Lars Bengtsson (ISQED, 2006)

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. - Minh Quang Do; Per Larsson-Edefors; Mindaugas Drazdziulis (DSD, 2007)

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. - Minh Quang Do; Mindaugas Drazdziulis; Per Larsson-Edefors; Lars Bengtsson (ISQED, 2007)

Overdrive Power-Gating Techniques for Total Power Minimization. - Mindaugas Drazdziulis; Per Larsson-Edefors; Lars J. Svensson (ISVLSI, 2007)