A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI. - Chung-Yu Wu; Ming-Dou Ker; Chung-Yuan Lee; Joe Ko (IEEE J. Solid State Circuits, 1992)

Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's. - Ming-Dou Ker; Chung-Yu Wu; Hun-Hsien Chang; Tao Cheng; Tain-Shun Wu (ISCAS, 1995)

Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC. - Ming-Dou Ker; Chung-Yu Wu; Tao Cheng; Hun-Hsien Chang (IEEE Trans. Very Large Scale Integr. Syst., 1996)

ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current. - Ming-Dou Ker (IEEE J. Solid State Circuits, 1997)

A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs. - Ming-Dou Ker; Hun-Hsien Chang; Chung-Yu Wu (IEEE J. Solid State Circuits, 1997)

Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection. - Ming-Dou Ker; Hun-Hsien Chang (CICC, 1998)

Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology. - Ming-Dou Ker; Jeng-Jie Peng (CICC, 1998)

Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: an overview. - Ming-Dou Ker (ICECS, 1998)

CMOS on-chip ESD protection design with substrate-triggering technique. - Ming-Dou Ker; Tung-Yang Chen; Chung-Yu Wu (ICECS, 1998)

New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's. - Ming-Dou Ker; Wen-Yu Lo; Chung-Yu Wu (CICC, 1999)

ESD buses for whole-chip ESD protection. - Ming-Dou Ker; Hun-Hsien Chang; Tung-Yang Chen (ISCAS (1), 1999)

Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications. - Ming-Dou Ker; Tung-Yang Chen; Chung-Yu Wu; Hun-Hsien Chang (ISCAS, 2000)

Mew diode string design with very low leakage current for using in power supply ESD clamp circuits. - Ming-Dou Ker; Wen-Yu Lo; Hun-Hsien Chang (ISCAS, 2000)

ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications. - Ming-Dou Ker; Tung-Yang Chen; Chung-Yu Wu; Hun-Hsien Chang (IEEE J. Solid State Circuits, 2000)

Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process. - Ming-Dou Ker; Wen-Yu Lo (IEEE J. Solid State Circuits, 2000)

Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process. - Ming-Dou Ker; Che-Hao Chuang; Wen-Yu Lo (ICECS, 2001)

Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. - Ming-Dou Ker; Hsin-Chin Jiang; Jeng-Jie Peng; Tzay-Luen Shieh (ICECS, 2001)

ESD test methods on integrated circuits: an overview. - Ming-Dou Ker; Jeng-Jie Peng; Hsin-Chin Jiang (ICECS, 2001)

Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes. - Ming-Dou Ker; Tung-Yang Chen (ISCAS (4), 2001)

ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique. - Ming-Dou Ker; Tung-Yang Chen; Chung-Yu Win (ISCAS (4), 2001)

Design on ESD Protection Circuit with Very Low and Constant Input Capacitance. - Tung-Yang Chen; Ming-Dou Ker (ISQED, 2001)

Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. - Ming-Dou Ker; Wen-Yu Lo; Tung-Yang Chen; Howard Tang; S.-S. Chen; Mu-Chun Wang (ISQED, 2001)

On-chip ESD protection design by using polysilicon diodes in CMOS process. - Ming-Dou Ker; Tung-Yang Chen; Tai-Ho Wang; Chung-Yu Wu (IEEE J. Solid State Circuits, 2001)

Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard. - Ming-Dou Ker; Yu-Yu Sung (Microelectron. Reliab., 2001)

ESD protection circuits with novel MOS-bounded diode structures. - Ming-Dou Ker; Che-Hao Chuang (ISCAS (5), 2002)

On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process. - Ming-Dou Ker; Kuo-Chun Hsu (ISCAS (5), 2002)

Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. - Jeng-Jie Peng; Ming-Dou Ker; Hsin-Chin Jiang (ISCAS (5), 2002)

ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process. - Ming-Dou Ker; Chien-Hui Chuang; Kuo-Chun Hsu; Wen-Yu Lo (ISQED, 2002)

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers. - Ming-Dou Ker; Chien-Hui Chuang (IEEE J. Solid State Circuits, 2002)

ESD protection design for CMOS RF integrated circuits using polysilicon diodes. - Ming-Dou Ker; Chyh-Yih Chang (Microelectron. Reliab., 2002)

Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits. - Ming-Dou Ker; Chien-Ming Lee (ISCAS (1), 2003)

Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit. - Ming-Dou Ker; Chia-Sheng Tsai (ISCAS (5), 2003)

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. - Ming-Dou Ker; Hsin-Chyh Hsu; Jeng-Jie Peng (ISQED, 2003)

Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC. - Ming-Dou Ker; Jeng-Jie Peng; Hsin-Chin Jiang (ISQED, 2003)

Substrate-triggered ESD protection circuit without extra process modification. - Ming-Dou Ker; Tung-Yang Chen (IEEE J. Solid State Circuits, 2003)

Latchup-free ESD protection design with complementary substrate-triggered SCR devices. - Ming-Dou Ker; Kuo-Chun Hsu (IEEE J. Solid State Circuits, 2003)

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. - I-Cheng Lin; Chih-Yao Huang; Chuan-Jane Chao; Ming-Dou Ker (Microelectron. Reliab., 2003)

Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC. - Wen-Yu Lo; Ming-Dou Ker (Microelectron. Reliab., 2003)

Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology. - Che-Hao Chuang; Ming-Dou Ker (ISCAS (2), 2004)

A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes. - Ming-Dou Ker; Shih-Lun Chen; Chia-Sheng Tsai (ISCAS (1), 2004)

ESD protection design for IC with power-down-mode operation. - Ming-Dou Ker; Kun-Hsien Lin (ISCAS (2), 2004)

Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes. - Ming-Dou Ker; Wen-Yi Chen (ISQED, 2004)

Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. - Ming-Dou Ker; Wei-Jen Chang; Wen-Yu Lo (ISQED, 2004)

Design on ESD protection scheme for IC with power-down-mode operation. - Ming-Dou Ker; Kun-Hsien Lin (IEEE J. Solid State Circuits, 2004)

Design optimization of ESD protection and latchup prevention for a serial I/O IC. - Chih-Yao Huang; Wei-Fang Chen; Song-Yu Chuan; Fu-Chien Chiu; Jeng-Chou Tseng; I-Cheng Lin; Chuan-Jane Chao; Len-Yi Leu; Ming-Dou Ker (Microelectron. Reliab., 2004)

New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation. - Ming-Dou Ker; Jung-Sheng Chen; Ching-Yun Chu (ISCAS (4), 2005)

Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications. - Ming-Dou Ker; Shih-Lun Chen; Chia-Sheng Tsai (ISCAS (2), 2005)

ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. - Kun-Hsien Lin; Ming-Dou Ker (ISCAS (2), 2005)

A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device. - Ming-Dou Ker; Jung-Sheng Chen; Ching-Yun Chu (IEICE Trans. Electron., 2005)

MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process. - Ming-Dou Ker; Kun-Hsien Lin; Che-Hao Chuang (IEICE Trans. Electron., 2005)

The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs. - Ming-Dou Ker; Kun-Hsien Lin (IEEE J. Solid State Circuits, 2005)

ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology. - Ming-Dou Ker; Kun-Hsien Lin (IEEE J. Solid State Circuits, 2005)

Investigation on seal-ring rules for IC product reliability in 0.25-mum CMOS technology. - Shih-Hung Chen; Ming-Dou Ker (Microelectron. Reliab., 2005)

A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals. - Shih-Lun Chen; Ming-Dou Ker (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit. - Ming-Dou Ker; Hsin-Chyh Hsu (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs. - Ming-Dou Ker; Cheng-Cheng Yen; Pi-Chia Shih (CICC, 2006)

Low-Power Wordline Voltage Generator for Low-Voltage Flash Memory. - Tzu-Ming Wang; Ming-Dou Ker; Steve Yeh; Ya-Chun Chang (ICECS, 2006)

System-Level ESD Protection Design with On-Chip Transient Detection Circuit. - Cheng-Cheng Yen; Ming-Dou Ker; Pi-Chia Shih (ICECS, 2006)

Design on new tracking circuit of I/O buffer in 0.13µm cell library for mixed-voltage application. - Zi-Ping Chen; Che-Hao Chuang; Ming-Dou Ker (ISCAS, 2006)

New matching methodology of low-noise amplifier with ESD protection. - Bo-Shih Huang; Ming-Dou Ker (ISCAS, 2006)

Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications. - Ming-Dou Ker; Chien-Hua Wu (ISCAS, 2006)

Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask. - Hsin-Chyh Hsu; Ming-Dou Ker (ISQED, 2006)

Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology. - Tai-Xiang Lai; Ming-Dou Ker (ISQED, 2006)

ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS. - Ming-Dou Ker; Wei-Jen Chang; Chang-Tzu Wang; Wen-Yi Chen (ISSCC, 2006)

Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique. - Ming-Dou Ker; Shih-Lun Chen (IEEE J. Solid State Circuits, 2006)

Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices. - Ming-Dou Ker; Jia-Huei Chen (IEEE J. Solid State Circuits, 2006)

Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes. - Ming-Dou Ker; Shih-Lun Chen; Chia-Sheng Tsai (IEEE J. Solid State Circuits, 2006)

Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology. - Shih-Hung Chen; Ming-Dou Ker (Microelectron. Reliab., 2006)

ESD robustness of thin-film devices with different layout structures in LTPS technology. - Chih-Kang Deng; Ming-Dou Ker (Microelectron. Reliab., 2006)

Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board. - Kun-Hsien Lin; Ming-Dou Ker (Microelectron. Reliab., 2006)

New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation. - Ming-Dou Ker; Jung-Sheng Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process. - Ming-Dou Ker; Wen-Yi Chen; Kuo-Chun Hsu (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors. - Ming-Dou Ker; Shih-Lun Chen; Chia-Sheng Tsai (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations. - Ming-Dou Ker; Kun-Hsien Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

CMOS Power Amplifier with ESD Protection Design Merged in Matching Network. - Yu-Da Shiu; Bo-Shih Huang; Ming-Dou Ker (ICECS, 2007)

Design of 2?VDD-Tolerant I/O Buffer with Considerations of Gate-Oxide Reliability and Hot-Carrier Degradation. - Hui-Wen Tsai; Ming-Dou Ker (ICECS, 2007)

A New Architecture for Charge Pump Circuit Without Suffering Gate-Oxide Reliability in Low-Voltage CMOS Processes. - Tzu-Ming Wang; Wan-Yi Shen; Ming-Dou Ker (ICECS, 2007)

Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology. - Ming-Dou Ker; Hung-Tai Liao (ISCAS, 2007)

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. - Yuan-Wen Hsiao; Ming-Dou Ker; Po-Yen Chiu; Chun Huang; Yuh-Kuang Tseng (SoCC, 2007)

Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology. - Ming-Dou Ker; Shih-Hung Chen (IEEE J. Solid State Circuits, 2007)

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits. - Shih-Hung Chen; Ming-Dou Ker (Microelectron. Reliab., 2007)

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology. - Ming-Dou Ker; Wei-Jen Chang (Microelectron. Reliab., 2007)

An Output Buffer for 3.3-V Applications in a 0.13- μħbox m 1/2.5-V CMOS Process. - Shih-Lun Chen; Ming-Dou Ker (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes. - Ming-Dou Ker; Shih-Lun Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration. - Wen-Yi Chen; Ming-Dou Ker; Yeh-Jen Huang; Yeh-Ning Jou; Geeng-Lih Lin (APCCAS, 2008)

An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process. - Yuan-Wen Hsiao; Ming-Dou Ker (CICC, 2008)

Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process. - Ting-Chou Lu; Ming-Dou Ker; Hsiao-Wen Zan; Chun-Hung Kuo; Chun-Huai Li; Yao-Jen Hsieh; Chun-Ting Liu (CICC, 2008)

Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology. - Shih-Hung Chen; Ming-Dou Ker (ICECS, 2008)

Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process. - Ming-Dou Ker; Tzu-Ming Wang; Fang-Ling Hu (ICECS, 2008)

On-glass digital-to-analog converter with gamma correction for panel data driver. - Tzu-Ming Wang; Yu-Hsuan Li; Ming-Dou Ker (ICECS, 2008)

ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. - Ming-Dou Ker; Chun-Yu Lin 001; Guo-Xuan Meng (ISCAS, 2008)

2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue. - Ming-Dou Ker; Tzu-Ming Wang; Hung-Tai Liao (ISCAS, 2008)

Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process. - Jung-Sheng Chen; Ming-Dou Ker (IEICE Trans. Electron., 2008)

Low-Capacitance and Fast Turn-on SCR for RF ESD Protection. - Chun-Yu Lin 001; Ming-Dou Ker; Guo-Xuan Meng (IEICE Trans. Electron., 2008)

Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test. - Ming-Dou Ker; Cheng-Cheng Yen (IEEE J. Solid State Circuits, 2008)

Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices. - Ming-Dou Ker; Yan-Liang Lin (CICC, 2009)

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS. - Ming-Dou Ker; Chang-Tzu Wang (CICC, 2009)

Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection. - Wen-Yi Chen; Ming-Dou Ker; Yeh-Ning Jou; Yeh-Jen Huang; Geeng-Lih Lin (ISCAS, 2009)

On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process. - Ming-Dou Ker; Po-Yen Chiu; Fu-Yi Tsai; Yeong-Jar Chang (ISCAS, 2009)

Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits. - Ming-Dou Ker; Yuan-Wen Hsiao (IEICE Trans. Electron., 2009)

Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology. - Chang-Tzu Wang; Ming-Dou Ker (IEEE J. Solid State Circuits, 2009)

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process. - Yuan-Wen Hsiao; Ming-Dou Ker (Microelectron. Reliab., 2009)

Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs. - Shih-Hung Chen; Ming-Dou Ker (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology. - Tzu-Ming Wang; Ming-Dou Ker; Hung-Tai Liao (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. - Ming-Dou Ker; Che-Lun Hsu; Wen-Yi Chen (ISCAS, 2010)

2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. - Chun-Yu Lin 001; Ming-Dou Ker (ISCAS, 2010)

Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. - Chih-Ting Yeh; Ming-Dou Ker (IEEE J. Solid State Circuits, 2010)

Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology. - Shih-Hung Chen; Ming-Dou Ker (Microelectron. Reliab., 2010)

Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme. - Chun-Yu Lin 001; Ming-Dou Ker; Yuan-Wen Hsiao (Microelectron. Reliab., 2010)

Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation. - Hui-Wen Tsai; Ming-Dou Ker (Microelectron. Reliab., 2010)

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process. - Wen-Yi Chen; Ming-Dou Ker (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance. - Ming-Dou Ker; Cheng-Cheng Yen (IEEE Trans. Ind. Electron., 2010)

Modified LC-tank ESD protection design for 60-GHz RF applications. - Chun-Yu Lin 001; Li-Wei Chu; Shiang-Yu Tsai; Ming-Dou Ker; Tse-Hua Lu; Tsun-Lai Hsu; Ping-Fang Hung; Ming-Hsiang Song; Jeng-Chou Tseng; Tzu-Heng Chang; Ming-Hsien Tsai 002 (ECCTD, 2011)

Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. - Chih-Ting Yeh; Yung-Chih Liang; Ming-Dou Ker (ISCAS, 2011)

Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs. - Ming-Dou Ker; Wen-Yi Chen; Wuu-Trong Shieh; I-Ju Wei (IEEE J. Solid State Circuits, 2011)

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process. - Chun-Yu Lin 001; Li-Wei Chu; Ming-Dou Ker (Microelectron. Reliab., 2011)

Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process. - Yi-Hsin Weng; Hui-Wen Tsai; Ming-Dou Ker (Microelectron. Reliab., 2011)

Design of ESD protection for RF CMOS power amplifier with inductor in matching network. - Shiang-Yu Tsai; Chun-Yu Lin 001; Li-Wei Chu; Ming-Dou Ker (APCCAS, 2012)

Design of negative high voltage generator for biphasic stimulator with soc integration consideration. - Ya-Chun Huang; Ming-Dou Ker; Chun-Yu Lin 001 (BioCAS, 2012)

Live demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability. - Ming-Dou Ker; Wei-Ling Chen; Chun-Yu Lin 001 (BioCAS, 2012)

Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. - Li-Wei Chu; Chun-Yu Lin 001; Shiang-Yu Tsai; Ming-Dou Ker; Ming-Hsiang Song; Chewnpu Jou; Tse-Hua Lu; Jeng-Chou Tseng; Ming-Hsien Tsai 002; Tsun-Lai Hsu; Ping-Fang Hung; Tzu-Heng Chang (ISCAS, 2012)

New design of transient-noise detection circuit with SCR device for system-level ESD protection. - Ming-Dou Ker; Wan-Yen Lin (NEWCAS, 2012)

High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process. - Chun-Yu Lin 001; Yi-Ju Li; Ming-Dou Ker (NEWCAS, 2012)

New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. - Chih-Ting Yeh; Ming-Dou Ker (VLSI-DAT, 2012)

Investigation on CDM ESD events at core circuits in a 65-nm CMOS process. - Chun-Yu Lin 001; Tang-Long Chang; Ming-Dou Ker (Microelectron. Reliab., 2012)

Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications. - Chih-Ting Yeh; Ming-Dou Ker (Microelectron. Reliab., 2012)

New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology. - Chih-Ting Yeh; Ming-Dou Ker (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels. - Ming-Dou Ker; Cheng-Cheng Yen (IEEE Trans. Ind. Electron., 2012)

Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology. - Federico A. Altolaguirre; Ming-Dou Ker (ISCAS, 2013)

A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control. - Wei-Ming Chen; Herming Chiueh; Tsan-Jieh Chen; Chia-Lun Ho; Chi Jeng; Shun-Ting Chang; Ming-Dou Ker; Chun-Yu Lin 001; Ya-Chun Huang; Chia-Wei Chou; Tsun-Yuan Fan; Ming-Seng Cheng; et al. (ISSCC, 2013)

Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology. - Po-Yen Chiu; Ming-Dou Ker (SoCC, 2013)

Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. - Federico A. Altolaguirre; Ming-Dou Ker (VLSI-DAT, 2013)

Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits. - Hui-Wen Tsai; Ming-Dou Ker; Yi-Sheng Liu; Ming-Nan Chuang (VLSI-DAT, 2013)

Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. - Chih-Ting Yeh; Ming-Dou Ker (VLSI-DAT, 2013)

PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit. - Chih-Ting Yeh; Ming-Dou Ker (Microelectron. Reliab., 2013)

Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability. - Chun-Yu Lin 001; Wei-Ling Chen; Ming-Dou Ker (IEEE Trans. Biomed. Circuits Syst., 2013)

Design of 2 × VDD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × VDD Thin-Oxide Devices. - Ming-Dou Ker; Po-Yen Chiu (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

ESD protection design for wideband RF applications in 65-nm CMOS process. - Li-Wei Chu; Chun-Yu Lin 001; Ming-Dou Ker; Ming-Hsiang Song; Jeng-Chou Tseng; Chewnpu Jou; Ming-Hsien Tsai 002 (ISCAS, 2014)

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. - Kuan-Yu Lin; Ming-Dou Ker; Chun-Yu Lin 001 (ISCAS, 2014)

Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process. - Federico A. Altolaguirre; Ming-Dou Ker (MWSCAS, 2014)

A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. - Wei-Ming Chen; Herming Chiueh; Tsan-Jieh Chen; Chia-Lun Ho; Chi Jeng; Ming-Dou Ker; Chun-Yu Lin 001; Ya-Chun Huang; Chia-Wei Chou; Tsun-Yuan Fan; Ming-Seng Cheng; Yue-Loong Hsin; et al. (IEEE J. Solid State Circuits, 2014)

Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit. - Po-Yen Chiu; Ming-Dou Ker (Microelectron. Reliab., 2014)

SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance. - Ming-Dou Ker; Wan-Yen Lin; Cheng-Cheng Yen (Microelectron. Reliab., 2014)

On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection. - Che-Hao Chuang; Ming-Dou Ker (IEEE Trans. Ind. Electron., 2014)

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. - Seian-Feng Liao; Kai-Neng Tang; Ming-Dou Ker; Jia-Rong Yeh; Hwa-Chyi Chiou; Yeh-Jen Huang; Chun-Chien Tsai; Yeh-Ning Jou; Geeng-Lih Lin (ECCTD, 2015)

Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits. - Hui-Wen Tsai; Ming-Dou Ker (ECCTD, 2015)

ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC. - Chia-Tsen Dai; Ming-Dou Ker (SoCC, 2015)

Active ESD protection for input transistors in a 40-nm CMOS process. - Federico A. Altolaguirre; Ming-Dou Ker (VLSI-DAT, 2015)

ESD protection design for high-speed applications in CMOS technology. - Jie-Ting Chen; Chun-Yu Lin 001; Rong-Kun Chang; Ming-Dou Ker; Tzu-Chien Tzeng; Tzu-Chiang Lin (MWSCAS, 2016)

Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator. - Zhicong Luo; Ming-Dou Ker (NEWCAS, 2016)

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process. - Zhicong Luo; Ming-Dou Ker (IEEE Trans. Biomed. Circuits Syst., 2016)

Design considerations and clinical applications of closed-loop neural disorder control SoCs. - Chung-Yu Wu; Cheng-Hsiang Cheng; Yi-Huan Ou-Yang; Chiung-Ghu Chen; Wei-Ming Chen; Ming-Dou Ker; Chen-Yi Lee; Sheng-Fu Liang; Fu-Zen Shaw (ASP-DAC, 2017)

An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation. - Ting-Chou Lu; Ming-Dou Ker; Hsiao-Wen Zan (IEICE Trans. Electron., 2017)

A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration. - Ting-Chou Lu; Ming-Dou Ker; Hsiao-Wen Zan; Jen-Chieh Liu; Yu Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process. - Chun-Yu Lin 001; Rui-Hong Liu; Ming-Dou Ker (Microelectron. Reliab., 2017)

A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process. - Zhicong Luo; Ming-Dou Ker; Tzu-Yi Yang; Wan-Hsueh Cheng (IEEE Trans. Biomed. Circuits Syst., 2017)

Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process. - Zhicong Luo; Ming-Dou Ker; Wan-Hsueh Cheng; Ting-Yang Yen (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Design of Multiple-Charge-Pump System for Implantable Biomedical Applications. - Shiau-Pin Lin; Ming-Dou Ker (BioCAS, 2018)

Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications. - Chia-Chi Hsieh; Ming-Dou Ker (MWSCAS, 2018)

A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications. - Zhicong Luo; Ming-Dou Ker (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control. - Cheng-Hsiang Cheng; Ping-Yuan Tsai; Tzu-Yi Yang; Wan-Hsueh Cheng; Ting-Yang Yen; Zhicong Luo; Xin-Hong Qian; Zhi-Xin Chen; Tzu-Han Lin; Wei-Hong Chen; Wei-Ming Chen; Sheng-Fu Liang; et al. (IEEE J. Solid State Circuits, 2018)

Surge protection design with surge-to-digital converter for microelectronic circuits and systems. - Wen-Chieh Chen; Ming-Dou Ker (Microelectron. Reliab., 2018)

Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process. - Chun-Cheng Chen; Ming-Dou Ker (IRPS, 2019)

ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications. - Tao-Yi Hung; Ming-Dou Ker (ISCAS, 2019)

Guest Editorial: Special Issue on Selected Papers From IEEE ISCAS 2019. - Ming-Dou Ker; Maurizio Valle; Matthew L. Johnston (IEEE Trans. Biomed. Circuits Syst., 2019)

Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem. - Xin-Hong Qian; Yi-Chung Wu; Tzu-Yi Yang; Cheng-Hsiang Cheng; Hsing-Chien Chu; Wan-Hsueh Cheng; Ting-Yang Yen; Tzu-Han Lin; Yung-Jen Lin; Yu-Chi Lee; Jia-Heng Chang; Shih-Ting Lin; et al. (IEEE Trans. Biomed. Eng., 2019)

An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS. - Chi-Wei Liu; Yi-Lun Chen; Pei-Chun Liao; Shiau-Pin Lin; Ting-Wei Wang; Ming-Jie Chung; Po-Hung Chen; Ming-Dou Ker; Chung-Yu Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process. - Zhicong Luo; Li-Chin Yu; Ming-Dou Ker (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition. - Sung-Hao Wang; Yu-Kai Huang; Ching-Yuan Chen; Chia-Fone Lee; Chia-Hsiang Yang; Chung-Chih Hung; Chien-Hao Liu; Ming-Dou Ker; Chung-Yu Wu (A-SSCC, 2020)

Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals. - Yi-Hui Wu; Yi-Huan Ou-Yang; Chiung-Chu Chen; Chen-Yi Lee; Chung-Yu Wu; Ming-Dou Ker (EMBC, 2020)

Over-Voltage Protection on the CC Pin of USB Type-C Interface against Electrical Overstress Events. - Chao-Yang Ke; Ming-Dou Ker (IRPS, 2020)

Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications. - Ting-Yang Yen; Ming-Dou Ker (IEEE Trans. Biomed. Circuits Syst., 2020)

Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation. - Shiau-Pin Lin; Ming-Dou Ker (IEEE Trans. Circuits Syst., 2020)

Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. - Chao-Yang Chen; Jian-Hsing Lee; Karuna Nidhi; Tzer-Yaa Bin; Geeng-Lih Lin; Ming-Dou Ker (IRPS, 2021)

ROT-Harris: A Dynamic Approach to Asynchronous Interest Point Detection. - Shane Harrigan; Sonya A. Coleman; Ming-Dou Ker; Pratheepan Yogarajah; Zheng Fang 001; Chengdong Wu 001 (MVA, 2021)

Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events. - Han-Sheng Huang; Ming-Dou Ker (VLSI-DAT, 2021)

Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification. - Sung-Hao Wang; Yu-Kai Huang; Ching-Yuan Chen; Li-Yang Tang; Yen-Fu Tu; Po-Chih Chang; Chia-Fone Lee; Chia-Hsiang Yang; Chung-Chih Hung; Chien-Hao Liu; Ming-Dou Ker; Chung-Yu Wu (IEEE J. Solid State Circuits, 2021)

Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process. - Chia-Chi Hsieh; Ming-Dou Ker (IEEE Trans. Biomed. Circuits Syst., 2021)

Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control. - I-Hsuan Wu; Ming-Dou Ker (VLSI-DAT, 2022)

Investigation of Safe Operating Area on 4H-SiC 600V VDMOSFET with TLP and UIS Test Methods. - Chao-Yang Ke; Yu-Chia Tsui; Bing-Yue Tsui; Ming-Dou Ker (IRPS, 2023)

A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs. - Chi-Wei Huang; Chin-Kai Lai; Chung-Chih Hung; Chung-Yu Wu; Ming-Dou Ker (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-Modulation. - Chia-Chi Hsieh; Yi-Hui Wu; Ming-Dou Ker (IEEE Trans. Biomed. Circuits Syst., 2023)

Embedded Deep-Nwell Collector Used to Improve Latch-Up Immunity of Multi-Functional I/O Buffer with Indirect Power-Connected N-Well. - Chen-Wei Hsu; Ming-Dou Ker; Ping-Lin Chung; Chin-Tung Cheng; Chih-Ping Chen (IRPS, 2024)

A Versatile 8-Channel High Voltage Stimulator for Comprehensive Neural Stimulation. - Kuan-Ting Lin; Ming-Dou Ker (ISCAS, 2024)

Stimulation-Induced Artifact Removal of the Local Field Potential Through Hardware Design: Toward the Implantable Closed-Loop Deep Brain Stimulation. - Yi-Hui Wu; Hsiao-Chun Lin; Chi-Wei Huang; Chung-Yu Wu; Ming-Dou Ker (IEEE Access, 2024)

Design of CMOS Analog Front-End Local-Field Potential Chopper Amplifier With Stimulation Artifact Tolerance for Real-Time Closed-Loop Deep Brain Stimulation SoC Applications. - Chung-Yu Wu; Chi-Wei Huang; Yu-Wei Chen; Chin-Kai Lai; Chung-Chih Hung; Ming-Dou Ker (IEEE Trans. Biomed. Circuits Syst., 2024)

Latch-Up Over-Current Protection Design with Power Restarted Function. - Shih-Cheng Huang; Ming-Dou Ker (IRPS, 2025)

Improved Layout Style on Diode- Trigger SCR for Low-C ESD Protection. - Chen-Yu Liang; Ming-Dou Ker (IRPS, 2025)

Design of Linear Battery Charger with Self-Blocking Reverse Current Path for Biomedical Applications. - Wen-Hsiang Huang; Ming-Dou Ker (ISCAS, 2025)

SDLA-based Logarithmic Amplifier Integrated with Magnitude Discriminator and Time Discriminator for Real-Time ESD Event Detection. - Chang-Jiun Lai; Ming-Dou Ker (ISCAS, 2025)

Miniaturized Wirelessly-Powered Biphasic Current Stimulator for Implantable Neurostimulation. - Chang-Chun Yang; Ming-Dou Ker (ISCAS, 2025)