Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. - Bing-Chuan Bai; Chun-Lung Hsu; Ming-Hsueh Wu; Chen-An Chen; Yee-Wen Chen; Kun-Lun Luo; Liang-Chia Cheng; James Chien-Mo Li (Asian Test Symposium, 2013)

Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs. - Chen-An Chen; Yee-Wen Chen; Chun-Lung Hsu; Ming-Hsueh Wu; Kun-Lun Luo; Bing-Chuan Bai; Liang-Chia Cheng (Asian Test Symposium, 2013)

Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM. - Kun-Lun Luo; Ming-Hsueh Wu; Chun-Lung Hsu; Chen-An Chen (J. Electron. Test., 2016)