A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. - Ming-Hung Chang; Zong-Xi Yang; Wei Hwang (ISCAS, 2007)

Fuzzy neural network design with switching strategy for permanent-magnet synchronous motor speed controller. - Ming-Hung Chang; Hung-Ching Lu; Cheng-Hung Tsai (SMC, 2007)

A flexible two-layer external memory management for H.264/AVC decoder. - Chang-Hsuan Chang; Ming-Hung Chang; Wei Hwang (SoCC, 2007)

Reconfigurable Optical Add/Drop Multiplexer with 8.0 dB Net Gain Using Dual-Pass Amplified Scheme. - Shien-Kuei Liaw; Ming-Hung Chang; Chun-Jung Wang; Yi-Tseng Lin (IEICE Trans. Commun., 2007)

A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. - Li-Pu Chuang; Ming-Hung Chang; Po-Tsang Huang; Chih-Hao Kan; Wei Hwang (ISCAS, 2008)

A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. - Ming-Hung Chang; Li-Pu Chuang; I-Ming Chang; Wei Hwang (SoCC, 2008)

A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm. - Yi-Ming Chang; Ming-Hung Chang; Wei Hwang (SoCC, 2009)

High efficiency power management system for solar energy harvesting applications. - Ming-Hung Chang; Jung-Yi Wu; Wei-Chih Hsieh; Shang-Yuan Lin; You-Wei Liang; Wei Hwang (APCCAS, 2010)

Fully on-chip temperature, process, and voltage sensors. - Shi-Wen Chen; Ming-Hung Chang; Wei-Chih Hsieh; Wei Hwang (ISCAS, 2010)

Radial basis function neural network with sliding mode control for robotic manipulators. - Hung-Ching Lu; Cheng-Hung Tsai; Ming-Hung Chang (SMC, 2010)

A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. - Ming-Hung Chang; Yi-Te Chiu; Shu-Lin Lai; Wei Hwang (ISLPED, 2011)

Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation. - Ming-Hung Chang; Chung-Ying Hsieh; Mei-Wei Chen; Wei Hwang (ISLPED, 2011)

Self-organizing fuzzy neural network controller design. - Ming-Hung Chang; Hung-Ching Lu (SMC, 2011)

An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. - Wei-Hung Du; Ming-Hung Chang; Hao-Yi Yang; Wei Hwang (SoCC, 2011)

Adaptive self-constructing fuzzy neural network controller for hardware implementation of an inverted pendulum system. - Hung-Ching Lu; Ming-Hung Chang; Cheng-Hung Tsai (Appl. Soft Comput., 2011)

Design of the Self-Constructing Fuzzy Neural Network controller for a sliding door system. - Hung-Ching Lu; Ming-Hung Chang (IJCNN, 2012)

An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. - Mei-Wei Chen; Ming-Hung Chang; Yuan-Hua Chu; Wei Hwang (SoCC, 2012)

A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. - Wei-Hung Du; Po-Tsang Huang; Ming-Hung Chang; Wei Hwang (VLSI-DAT, 2012)

Parameter estimation of fuzzy neural network controller based on a modified differential evolution. - Hung-Ching Lu; Ming-Hung Chang; Cheng-Hung Tsai (Neurocomputing, 2012)

A 0.4 V 520 nW 990 μm2 Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS. - Ming-Hung Chang; Shang-Yuan Lin; Wei Hwang (J. Low Power Electron., 2012)

Design and Iso-Area Vmin Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS. - Ming-Hung Chang; Yi-Te Chiu; Wei Hwang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. - Ming-Hung Chang; Shang-Yuan Lin; Pei-Chen Wu; Olesya Zakoretska; Ching-Te Chuang; Kuan-Neng Chen; Chen-Chao Wang; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Wei Hwang (ISCAS, 2013)

A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. - Mei-Wei Chen; Ming-Hung Chang; Pei-Chen Wu; Yi-Ping Kuo; Chun-Lin Yang; Yuan-Hua Chu; Wei Hwang (SoCC, 2013)

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS. - Ching-Wei Wu; Ming-Hung Chang; Chia-Cheng Chen; Robin Lee; Hung-Jen Liao; Jonathan Chang (A-SSCC, 2014)

GM(1, 1;λ) with Constrained Linear Least Squares. - Ming-Feng Yeh; Ming-Hung Chang (Axioms, 2021)

A Unified Grey Riccati Model. - Ming-Feng Yeh; Ming-Hung Chang; Ching-Chuan Luo (Axioms, 2022)

Speed control of electric vehicle by using type-2 fuzzy neural network. - Ming-Hung Chang; Yi-Chao Wu (Int. J. Mach. Learn. Cybern., 2022)

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (ISSCC, 2024)

Conflict, dissonance and engagement in virtual communities. - Jao-Hong Cheng; Ming-Hung Chang; Zong-Heng Jheng; Albert Huang; Shang-Che Huang (Int. J. Serv. Stand., 2024)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)

A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)