A High Throughput-Rate Architecture for 8*8 2-D DCT. - Ming-Hwa Sheu; Jau-Yien Lee; Jhing-Fa Wang; An-Nan Suen; Lian-Ying Liu (ISCAS, 1993)

An Expandable Chip Desing for Gray-scale Morphological Operations. - Ming-Hwa Sheu; Jhing-Fa Wang; Jau-Yien Lee; Lian-Ying Liu (ISCAS, 1993)

The determination of the cycle length in high level synthesis. - Ming-Hwa Sheu; Yuan-Long Jeang; Jhing-Fa Wang; Jau-Yien Lee (Integr., 1993)

A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. - Che-Han Wu; Ming-Der Shieh; Chien-Hsing Wu 002; Ming-Hwa Sheu; Jia-Lin Sheu (ISCAS (1), 1999)

High-speed generation of LFSR signatures. - Ming-Der Shieh; Hsin-Fu Lo; Ming-Hwa Sheu (Asian Test Symposium, 2000)

An efficient approach for in-place scheduling of path metric update in Viterbi decoders. - Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu 002; Ming-Hwa Sheu (ISCAS, 2000)

A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. - Ming-Hwa Sheu; Ho-En Liao; Shih Tsung Kan; Ming-Der Shieh (ISCAS (4), 2001)

VLSI architecture of extended in-place path metric update for Viterbi decoders. - Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu 002; Ming-Hwa Sheu (ISCAS (4), 2001)

A Systematic Approach for Parallel CRC Computations. - Ming-Der Shieh; Ming-Hwa Sheu; Chung-Ho Chen; Hsin-Fu Lo (J. Inf. Sci. Eng., 2001)

Fast design approach for implementing the approximate squaring function. - Ming-Hwa Sheu; Su-Hon Lin (APCCAS (2), 2002)

Fast compensative design approach for the approximate squaring function. - Ming-Hwa Sheu; Su-Hon Lin (IEEE J. Solid State Circuits, 2002)

A Fast Additive Normalization Method for Exponential Computation. - Chichyang Chen; Rui-Lin Chen; Ming-Hwa Sheu (DSD, 2003)

An efficient VLSI design for a residue to binary converter for general balance moduli (2n-3, 2n+1, 2n-1, 2n+3). - Ming-Hwa Sheu; Su-Hon Lin; Chichyang Chen; Shyue-Wen Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Directional interpolation for field-sequential stereoscopic video. - Hsien-Huang P. Wu; Ming-Hwa Sheu; Tung-Yu Yang (ISCAS (3), 2005)

VLSI architecture design for a fast parallel label assignment in binary image. - Shyue-Wen Yang; Ming-Hwa Sheu; Hsien-Huang P. Wu; Hung-En Chien; Ping-Kuo Weng; Ying-Yih Wu (ISCAS (3), 2005)

Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw (PCM (1), 2005)

Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. - Yin-Tsung Hwang; Jin-Fa Lin; Ming-Hwa Sheu; Chia-Jen Sheu (APCCAS, 2006)

The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chih-Jen Wei (APCCAS, 2006)

Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1). - Su-Hon Lin; Ming-Hwa Sheu; Jing-Shiun Lin; Wen-Tsai Sheu (APCCAS, 2006)

Film-to-Video Conversion with Scene Cut Detection. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw; Ming-Che Chen (ICICIC (1), 2006)

A high speed and energy efficient full adder design using complementary & level restoring carry logic. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu; Cheng-Che Ho (ISCAS, 2006)

The VLSI design of de-interlacing with scene change detection. - Chung-Chi Lin; Chih-Jen Wei; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw (ISCAS, 2006)

Automatic Generation of Programmable Parallel CRC & Scrambler Designs. - Yin-Tsung Hwang; Jiun-Yan Chen; Ming-Hwa Sheu (SiPS, 2006)

The VLSI Design of Winscale for Digital Image Scaling. - Chung-Chi Lin; Zeng-Chuan Wu; Wen-Kai Tsai; Ming-Hwa Sheu; Huann-Keng Chiang (IIH-MSP, 2007)

Fast Fair Crossbar Scheduler for On-chip Router. - Shyue-Wen Yang; Ming-Hwa Sheu; Chun-Kai Yeh; Chih-Yuen Wen; Chih-Chieh Lin; Wen-Kai Tsai (ISCAS, 2007)

Low Power Multipliers Using Enhenced Row Bypassing Schemes. - Yin-Tsung Hwang; Jin-Fa Lin; Ming-Hwa Sheu; Chia-Jen Sheu (SiPS, 2007)

Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. - Su-Hon Lin; Ming-Hwa Sheu; Kuang-Hui Wang; Jun-Jie Zhu; Si-Ying Chen (SiPS, 2007)

A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chih-Jen Wei; Chishyan Liaw (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu; Cheng-Che Ho (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n, 2n+1-1, 2n-1). - Su-Hon Lin; Ming-Hwa Sheu; Chao-Hsiang Wang; Yuan-Ching Kuo (APCCAS, 2008)

Real-time FPGA architecture of extended linear convolution for digital image scaling. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Wen-Kai Tsai; Zeng-Chuan Wu (FPT, 2008)

A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Zeng-Chuan Wu; Jia-Yi Tu; Chia-Hung Chen (ICESS, 2008)

The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw; Zeng-Chuan Wu (ISCAS, 2008)

An efficient convolution interpolation kernel for digital image scaling. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw; Zeng-Chuan Wu (IEICE Electron. Express, 2008)

Low Complexity Dual-Mode Pulse Generator Designs. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Area-Time Efficient Modulo 2n - 1 Adder Design Using Hybrid Carry Selection. - Su-Hon Lin; Ming-Hwa Sheu (IEICE Trans. Inf. Syst., 2008)

Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1). - Su-Hon Lin; Ming-Hwa Sheu; Chao-Hsiang Wang (IEICE Trans. Inf. Syst., 2008)

High-performance very large scale integration architecture design for various-ratio image scaling. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw (J. Electronic Imaging, 2008)

VLSI Design of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection. - Su-Hon Lin; Ming-Hwa Sheu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Parallel 3-Pixel Labeling Method and its Hardware Architecture Design. - Shyue-Wen Yang; Ming-Hwa Sheu; Jun-Jie Lin; Chuang-Chun Hu; Tzu-Hsiung Chen; Shau-Yin Tseng (IAS, 2009)

Image Object Detection and Tracking Implementation for Outdoor Scenes on an Embedded Soc Platform. - Wen-Kai Tsai; Ming-Hwa Sheu; Ching-Lung Su; Jun-Jie Lin; Shau-Yin Tseng (IIH-MSP, 2009)

Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2p+k, 2p+1, 2p-1, 22p+1). - Yuan-Ching Kuo; Su-Hon Lin; Ming-Hwa Sheu; Jia-You Wu; Peng-Siang Wang (ISCAS, 2009)

FPGA implementation for image object detection system on NoCs. - Ming-Hwa Sheu; Shyue-Wen Yang; Wen-Sheng Huang; Siang-Min Siao (APCCAS, 2010)

Fast Texture-Based Object Tracking Algorithm on Embedded Platform. - Ming-Hwa Sheu; Wen-Kai Tsai; Chuang-Chun Hu; Chun-Heng Tsao (FCST, 2010)

Efficient Multi-Layer Background Model on Complex Environment for Foreground Object Detection. - Wen-Kai Tsai; Ming-Hwa Sheu; Chung-Chi Lin (IIH-MSP, 2010)

A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Low Power Pulse Generator Design Using Hybrid Logic. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

An Efficient Architecture of Extended Linear Interpolation for Image Processing. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw; Zeng-Chuan Wu; Wen-Kai Tsai (J. Inf. Sci. Eng., 2010)

Fast First-Order Polynomials Convolution Interpolation for Real-Time Digital Image Reconstruction. - Chung-Chi Lin; Ming-Hwa Sheu; Chishyan Liaw; Huann-Keng Chiang (IEEE Trans. Circuits Syst. Video Technol., 2010)

Efficient Color-Ingredient Particle Filter for Video Object Tracking. - Jian-Hui Chen; Wen-Kai Tsai; Ming-Hwa Sheu; Kai-Min Lin; Ho-En Liao (IBICA, 2011)

New Reverse Converter Design of Moduli Set {2n, 2n+1-1, 2n-1}. - Yuan-Ching Kuo; Ming-Hwa Sheu; Siang-Min Siao; Cheng-Yi Huang; Tzu-Hsiung Chen (IBICA, 2011)

Region-Based Background Subtraction for Complex Sense on Embedded Platforms. - Wen-Kai Tsai; Ming-Hwa Sheu; Chung-Chi Lin (IIH-MSP, 2012)

Low power 10-transistor full adder design based on degenerate pass transistor logic. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (ISCAS, 2012)

Fast image moving object segmentation based on block texture for embedded system implementation. - Shyue-Wen Yang; Ming-Hwa Sheu; Wen-Kai Tsai (ISPACS, 2012)

A robust background modeling and foreground object detection using color component analysis. - Wen-Kai Tsai; Ming-Hwa Sheu; Chung-Chi Lin; Ho-En Liao (SMC, 2012)

A hybrid pixel-based background model for image foreground object detection in complex sence. - Chung-Chi Lin; Wen-Kai Tsai; Ming-Hwa Sheu (TSP, 2012)

Block-Based Major Color Method for Foreground Object Detection on Embedded SoC Platforms. - Wen-Kai Tsai; Ming-Hwa Sheu; Chung-Chi Lin (IEEE Embed. Syst. Lett., 2012)

Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. - Yin-Tsung Hwang; Jin-Fa Lin; Ming-Hwa Sheu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A Computation Efficiency AND-CFAR for FMCW Radar Receiver. - Ho-En Liao; Guan-Yu Lin; Ming-Hwa Sheu; Siang-Min Siao; Sin-Siang Wan (IIH-MSP, 2013)

Fast Image Blending and Deghosting for Panoramic Video. - Chen-Hong Yuan; Jeng-Shyang Pan 001; Ming-Hwa Sheu; Tzu-Hsiung Chen (IIH-MSP, 2013)

Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2n + k, 2n + 1, 2n - 1, 22n + 1}. - Ming-Hwa Sheu; Yuan-Ching Kuo; Su-Hon Lin; Siang-Min Siao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Feature Points Based Video Object Tracking for Dynamic Scenes and Its FPGA System Prototyping. - Yin-Tsung Hwang; Bing Cheng Tsai; Yu-Ting Pai; Ming-Hwa Sheu (IIH-MSP, 2014)

Ultra Low Power Circuit Design Based on Adiabatic Logic. - Chi-Chia Sun; Cheng Chih Wang; Ming-Hwa Sheu (IIH-MSP, 2014)

High Dynamic Range Image Based on Block-Based Edge Strength for Embedded System Design. - Wen-Kai Tsai; Chang Jie Lai; Ming-Hwa Sheu; Tsu Hsiung Chen (IIH-MSP, 2014)

Extendable multi-pixel object labeling for digital image. - Ming-Hwa Sheu; Shyue-Wen Yang; Tzu-Hsiung Chen (ICCE-TW, 2015)

Efficient object motion detection based on RGB-D image. - Yi-Hua Wang; Ming-Hwa Sheu; Chi-Chia Sun (ICCE-TW, 2015)

High efficient hardware allocation framework of arbitrary inverse transform coding blocks in H.265. - Chi-Chia Sun; Heng-Chi Lai; Sin-Kun Lin; Ming-Hwa Sheu; Mladen Berekovic (ISPACS, 2015)

Edge-based moving object tracking algorithm for an embedded system. - Kai Xiang Yang; Ming-Hwa Sheu (APCCAS, 2016)

Intelligent system design for variable color temperature LED street light. - Ming-Hwa Sheu; Li Hung Chang; Shih-Chang Hsia; Chi-Chia Sun (ICCE-TW, 2016)

Object detection using adaptive block-based background model. - Wen-Kai Tsai; Jian-Hui Chen; Ming-Hwa Sheu; Chi-Chia Sun (ICCE-TW, 2016)

Single image fog removal algorithm based on an improved dark channel prior method. - Chi-Chia Sun; Heng-Chi Lai; Ming-Hwa Sheu; Yi-Hsing Huang (ISPACS, 2016)

New adaptable three-moduli set {2n+k, 2n - 1, 2n-1 - 1} for residue number system-based finite impulse response implementation. - Ming-Hwa Sheu; Siang-Min Siao; Yin-Tsung Hwang; Chi-Chia Sun; You-Ping Lin (IEICE Electron. Express, 2016)

High-performance reverse converter design for the new four-moduli Set {22n, 2n+1, 2n/2+1, 2n/2-1}. - Siang-Min Siao; Ming-Hwa Sheu; Shao-Yu Wang (DSC, 2017)

A new fall detection algorithm based on depth information using RGB-D camera. - Chi-Chia Sun; Ming-Hwa Sheu; Yu-Cheng Syu (ISPACS, 2017)

Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes. - Jin-Fa Lin; Ming-Hwa Sheu; Yin-Tsung Hwang; Chen-Syuan Wong; Ming-Yan Tsai (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. - Ming-Yan Tsai; Po-Yu Kuo; Jin-Fa Lin; Ming-Hwa Sheu (ISCAS, 2018)

Implementation of FPGA-based Accelerator for Deep Neural Networks. - Tsung-Han Tsai 001; Yuan-Chen Ho; Ming-Hwa Sheu (DDECS, 2019)

Low-Power Counter-Based Delay Line Design For DPWM. - Cheng-Jie Yang; Ming-Jie Li; Chen-Yueh Liu; Ming-Hwa Sheu; Chi-Chia Sun (ICCE-TW, 2019)

The Image Shape Recovery on Communication Data Lost Damage. - Shih-Chang Hsia; Ming-Hwa Sheu; Cheng Hung Hsiao (ICUFN, 2019)

Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design. - Po-Yu Kuo; Chia-Hsin Hsieh; Jin-Fa Lin; Ming-Hwa Sheu; Yi-Ting Hung (IEICE Trans. Electron., 2019)

A Fast Non-Overlapping Multi-Camera People Re-Identification Algorithm and Tracking Based on Visual Channel Model. - Chi-Chia Sun; Ming-Hwa Sheu; Jui-Yang Chi; Yan-Kai Huang (IEICE Trans. Inf. Syst., 2019)

Real-Time Lighter Sound Recognition System for IoT Applications. - Yu-Sheng Yang; Che-Wei Chen; Ming-Hwa Sheu; Szu-Hong Wang; Tzu-Hsiung Chen (ICCE-TW, 2020)

Cost-Effective LED Dimming Driver With Single Chip Design for Smart Lighting System. - Shih-Chang Hsia; Ming-Hwa Sheu; Jyun-Jia Ciou (IEEE Access, 2020)

AIoT-based Audio Recognition System for Smart Home Applications. - Bo-Wei Chen; Yu-Syuan Jhang; Hao-Ting Pai; Szu-Hong Wang; Ming-Hwa Sheu; Tzu-Hsiung Chen (ICCE-TW, 2021)

A Novel Bird Detection and Identification based on DPU processor on PYNQ FPGA. - Guan-Zhou Lin; Hoang Minh Nguyen; Chi-Chia Sun; Po-Yu Kuo; Ming-Hwa Sheu (ICCE-TW, 2021)

Font-End Integrated Circuit Design for Plant Physiological Sensing. - En-Chi Yang; Ming Jie Lee; Wen-Ho Juang; Ming-Hwa Sheu; Shin-Chi Lai (ICCE-TW, 2021)

Software and Hardware Integration System Design with Fruit Identification for Smart Electronic Scale Applications. - Wei-Yu Zhu; Wing-Kwong Wong; S. M. Salahuddin Morsalin; Szu-Hong Wang; Ming-Hwa Sheu (ICCE-TW, 2021)

Real-time Stereo Television Broadcasting System. - Shih-Chang Hsia; Szu-Hong Wang; Ho-Cheng Tsai; Ming-Hwa Sheu (ICCE, 2021)

Fast-transient high-voltage buck-boost DC-DC conversion with low overshoot. - Shih-Chang Hsia; Ming-Hwa Sheu; Jhih-Jian Jhou (Microelectron. J., 2021)

FGSC: Fuzzy Guided Scale Choice SSD Model for Edge AI Design on Real-Time Vehicle Detection and Class Counting. - Ming-Hwa Sheu; S. M. Salahuddin Morsalin; Jia-Xiang Zheng; Shih-Chang Hsia; Cheng-Jian Lin; Chuan-Yu Chang (Sensors, 2021)

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications. - Ming-Hwa Sheu; Chang-Ming Tsai; Ming-Yan Tsai; Shih-Chang Hsia; S. M. Salahuddin Morsalin; Jin-Fa Lin (Sensors, 2021)

Integration Design of Portable ECG Signal Acquisition With Deep-Learning Based Electrode Motion Artifact Removal on an Embedded System. - Yu-Syuan Jhang; Szu-Ting Wang; Ming-Hwa Sheu; Szu-Hong Wang; Shin-Chi Lai (IEEE Access, 2022)

Hardware Accelerator Design of DCT Algorithm With Unique-Group Cosine Coefficients for Mel-Scale Frequency Cepstral Coefficients. - Shin-Chi Lai; Ying-Hsiu Hung; Yi-Chang Zhu; Szu-Ting Wang; Qi-Xian Huang; Ming-Hwa Sheu; Wen-Ho Juang (IEEE Access, 2022)

Lightweight Denoising Autoencoder Design for Noise Removal in Electrocardiography. - Ming-Hwa Sheu; Yu-Syuan Jhang; Yen-Ching Chang; Szu-Ting Wang; Chuan-Yu Chang; Shin-Chi Lai (IEEE Access, 2022)

FIBS-Unet: Feature Integration and Block Smoothing Network for Single Image Dehazing. - Ming-Hwa Sheu; S. M. Salahuddin Morsalin; Szu-Hong Wang; Yu-Teng Shen; Shih-Chang Hsia; Chuan-Yu Chang (IEEE Access, 2022)

FHI-Unet: Faster Heterogeneous Images Semantic Segmentation Design and Edge AI Implementation for Visible and Thermal Images Processing. - Ming-Hwa Sheu; S. M. Salahuddin Morsalin; Szu-Hong Wang; Lin-Keng Wei; Shih-Chang Hsia; Chuan-Yu Chang (IEEE Access, 2022)

A Low-Complexity Convolution Network for Upscale Super-Resolution Image. - Shih-Chang Hsia; Szu-Hong Wang; Ming-Hwa Sheu; Wei-Chien Yuan (ICKII, 2023)

Unique Feature Extraction and Consistency Network for Skeleton Body Keypoints Configuration and Enhancement. - Ming-Hwa Sheu; S. M. Salahuddin Morsalin; Yi-Wen Chang; Szu-Hong Wang; Chung-Chian Hsu; Shin-Chi Lai (ICKII, 2023)

Heart Valve Disease Recognition Using Phonocardiogram Signal Based on A Lightweight Convolution Neural Network. - Yen-Ching Chang; Szu-Ting Wang; Ying-Hsiu Hung; Yao-Feng Liang; Ming-Hwa Sheu; Shin-Chi Lai (ISOCC, 2023)

Convolutional Neural Network-based Keyword Classification for Mixer Control. - Ying-Hsiu Hung; Yen-Ching Chang; Suz-Ting Wang; Jeng-Dao Lee; Wen-Ho Juang; Ming-Hwa Sheu; Shin-Chi Lai (ISOCC, 2023)

Fast Measurement of Impedance Calculation for Electrochemical Impedance Spectroscopy. - En-Chi Yang; Suz-Ting Wang; Kusn-Lin Liu; Wen-Ho Juang; Ming-Hwa Sheu; How-Chiun Wu; Shin-Chi Lai (ISOCC, 2023)

Improvement of Human Pose Estimation and Processing With the Intensive Feature Consistency Network. - Ming-Hwa Sheu; S. M. Salahuddin Morsalin; Chung-Chian Hsu; Shin-Chi Lai; Szu-Hong Wang; Chuan-Yu Chang (IEEE Access, 2023)

Portable RDFT-Based EIS System Design With a Low-Complexity Impedance Calculation. - Wen-Ho Juang; En-Chi Yang; Szu-Ting Wang; Ming-Hwa Sheu; How-Chiun Wu; Shin-Chi Lai (IEEE Trans. Instrum. Meas., 2023)

Low-Complexity RDFT-Based Impedance Calculation for Enhanced EIS Analysis. - Wen-Ho Juang; Li-Chuan Hsu; Hau-Ping Chen; En-Chi Yang; Ming-Hwa Sheu (APCCAS, 2024)

DMCGF Dehazing Neural Network Design for Edge-AI Implementation. - Kuo-Yi Chang; Kun-Lin Li; Ming-Hwa Sheu; Szu-Hong Wang (CyberSciTech, 2024)

Integrating Noise Classification and Speech Enhancement Model for Hearing Aids. - Ying-Hsiu Hung; Yen-Ching Chang; Shin-Chi Lai; Wen-Ho Juang; Ming-Hwa Sheu; Jeng-Dao Lee (ISOCC, 2024)

High Precision, Low Complexity, and Fast Calculation Based on Hybrid Recursive DFT and FFT Algorithms for Electrochemical Impedance Spectroscopy System. - Ming-Hwa Sheu; En-Chi Yang; Szu-Ting Wang; Wen-Ho Juang; Shin-Chi Lai (IEEE Trans. Instrum. Meas., 2024)

VLSI Architecture Design for Compact Shortcut Denoising Autoencoder Neural Network of ECG Signal. - Shin-Chi Lai; Szu-Ting Wang; S. M. Salahuddin Morsalin; Jia-He Lin; Shih-Chang Hsia; Chuan-Yu Chang; Ming-Hwa Sheu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)